Wistron TM-C100-tm-C100_sch.pdf

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TM100
Project Code :
91.48R01.001
CPU DC/DC
PCB P/N :
01201-1
PCB : 48.48R01.001
Switching Power
MAX1718/MAX1714
OUTPUTS
INPUTS
CPU
PIII TUALATIN
ULV 700MHz~
PCB LAYER
3D3V_S0/2D5V_S0
CLOCK
Genertor
DCBATOUT
VCC_CORE_S0
L1:COMPONENT
VCCT_S0
FCBGA
L2:GND
PAGE:27,28
ICS9248-61
Page:3
Page:3,4
L3:SIGNAL
HOST BUS
100MHz
L4:SIGNAL
DC/DC&CHARGER
5V_S0
L5:GND
Switching Power
2D5V_S3/3D3V_S3
/2D5VRD_S3
VGA
CRT
MAX1632/OZT05J02
L6:VCC
SDRAM
SDRAM*2
3D3V_S3
Page:10
+3.3V/M+3V/+2.5V/M+2.5V/+5V
L7:SIGNAL
100MHz
INPUTS
OUTPUTS
33MHz
SMI SM722
L8:SIGNAL
3D3V_S0
3D3V_S5AC
LCD
L9:GND
DCBATOUT
Page:8
CORE LOGIC
Intel 82443MX
Page:9
3D3V1_S5AC
Page:11
L10:COMPONENT
3D3V_S3
3D3V_S0
5V_S0
Page:7
+3.3V/+5V/+12V
SMART Card
SLOT *1
Page:15
5V_S0
IDE BUS
Ultra 33
12V_S0
HDD
CARDBUS
AD+
BT+
Page:13
O2 OZ711
TARZEN
PAGE:29,30,31
/32,33
CARDBUS
SLOT *1
Page:15
Page:14
OTHER DC/DC
MAX1792/G913
OUTPUTS
PCI BUS
XD BUS
INPUTS
3D3V_S0
2D5V_S0
5V_S0
5V_S3
5V_S0
5V_S0
LAN_3D3V_S5AC/
LAN_2D5V_S5AC/
3D3V_S5AC
3D3V_S0
DEBUG
PORT
2D5V_S0
1D5V_S0
SIO
KBC
BIOS
1D8V_S0
LAN
MINIPCI
IEEE 1394
NS 97338
M38869
ROM
RTL8100BL
802.11
TI TSB43AB21
Page:16
3D3V_S3
2D5V_S3
Page:25
Page:23
Page:24
Page:27
Page:17,18
Page:19
PAGE:28
AC-LINK
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
3D3V_S0
5V_S0
5V_S0
5V_S3
5V_S0
3D3V_S0/5V_S0
5VA_S0
Touch
FIR
DIGITIZER
Page:11
INTKB
USB
PORT
MODEM
AC 97
Title
Pad
IRMS6452
Daughter
Card
Codec
System Block Diagram
Page:23
Page:23
Page:26
0,1
Page:26
CS4299-XQ
Size
Document Number
Rev
Page:19
Page:20,21,22
A4
TM100
-1
Date:
Thursday, April 04, 2002
S heet
1
of
35
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1. Support S3 State (Suspend To RAM):
* SC -> SD
Page 6:
1.Change Q26 from BSS138 to MMBT3904
Page 7 :
2.GPIO9 : Replace 802.11LED# with OBLAN-80211#
3.Add smith trigger and debounce RC to solve 100uS drop of SUSB#
Page 10:
4.Change VGA connecter for ME request
Page 11:
5.Change U88-1 control pin from U50-2 to BL2#
6.Replace digitizer reset signal from SUSB# to PCIRST2#
7.Add R564 to limit the current
Page 12:
8.U51-1control signal changed from 3D3V_S0 to PRE_SUSC#
Page 13:
9.Add D34 to prevent park voltage of HDD under -0.3V
Page 14:
10.Add DTC124EKA and dummy R546 to be the gate of PME# of OZ711.
Page 16:
11.Change 1394 connecter for ME request
Page 17:
12.Use U90 as the gate to control PCIRST2# to OBLAN and PL 10K to PCIRST2#_LAN
13.Replace the L15 to R563(0R3) for vendor request.
14.Add 100K to PL the U70-74 to solve the wake on LAN.
Page 18:
15.Dummy BC38, R526, R527, R528 for vendor request.
Page 19:
16.Modify the 802.11L_ACT from CN18 pin12 to pin11.
17.Use U91 as the gate to control PCIRST2# to 802.11 and PL 10K to PCIRST2#_80211
18.Add 10K to pull up BAN_PME# to 3D3V_S5
Page 20:
19.Add 3 open-gapes for EMI request.
Page 21:
20.Add DC bias PH 4.7K to internal MIC
Page 22:
21.Update Audio Jack for ME request
Page 23:
22.Modify the email-led control method because there is no GND on KB for KB matrix to PL.
23.Use 7474 to keep the reset of KBC while in S3.
24.Use the DTC124EKA and RB731U to prevent the leakage between KBC and Banister while in S3.
Page 24:
25.Add helf smith-trigger to 5 button.
Page 26:
26.Delet F2 and change it to 0.75A
27.Add Beads between USB conn. and bypass C for EMI request
Page 27:
28.Use CC_CPUSTP to drive CC_DPSLP#
29.Change R93 from 0R to 4.7R for EMI request
Page 28:
30.Change R532 from 0R to 4.7R
Page 29:
31.Parallel 47KR to BC55
32.For SKIP mode , modify the BC5 and BC140 to 47PF and add 100PF to replace R24 and R37.
33.Change R26,R27,R13 and R36 from 0R to 4.7R for EMI request.
Page 30:
34.Add smith trigger and debounce RC to solve 100uS drop of SUSC#
Page 31:
35.Add bypass 0.1uF between AC Jack and bead for EMI request .
36.Change R3 from 10K to 2.2K
Page 32:
37.Change R97 from 15mR to 18mR for current limit of adaptor.
38.Change R258 and R96 from 0R to 4.7R for EMI request
Page 33:
39.Add 10KR to Pull BL2# to 3D3V_S3
40.Change R261 from 10K to 2.2K
41.Change U44 from MAX1615 to LP2951 for cost down
Page 35:
42.DEL: K8, K9, K10, and K11
43.Add: K15
SD -> SE
Page 10:
1 Add F2 for safety request.
Page 13:
2.Remove R335 for the driving high is not enough.
Page 27:
3. Del R567
Page 32:
4.Change R97 from 64.R0185.A71 to 64.R0185781 because it might generate shortage due to the pad of compoment is too large
SE => -1
Page 7:
1. Change VCC of 82440MX from 3D3V_S0 to 3D3V_S3.
2. Change power plane of R139 from 5V_S0 to 5V_S3
3. Change power plane of D9 from 3D3V_S0 to 3D3V_S3
Page 20:
4. Reserve R569 and R570 to use different Codec.
Page 22:
5. Tune R380, R381, R383, and R383 for audio performance.
Page 30:
6. Add U21D between U35 and U60C.
Wake Up Event
Chip Controller
No
Description
1
2
PME#_RSM(WOL)
LAN Controller RTL8100L Magic Packet/ Wake Up Frame
PWRBTN#_5RSM
Banister
Wake Event from User
3
LID
KBC
4
Ring IN
MDC
5
Any Key
KBC
6
BL2#
KBC
2. Change notice :
* Before SMT of SA::
1>0R3-0-U ( 63.R0004.151) DEL: R260, R211, R214 ADD: R261, R209, R216, R263
2>Charger firmware U48 from P/N:71.12509.00A(PIC) to P/N:71.00012.00A(ATMEL)
* SA - > SB:
1>Swap smart card connecter and use this one. P/N: 20.K0090.012
2>Dummy the 5 resisters of VGA: R46, R238, R240, R241, R242 - P/N:63.47234.151
3>Modify the U4-4 from 2D5V_S0 to 2D5V_S3
4>Change the Q6 from 2N7002 - P/N:84.27002.031 to TP0610 -P/N: 84.00610.031 , then swap D and S
5>Change R6 from 10K - 63.10334.151 to 1K - 63.10234.151
6>Connect R49 and R52 LVDSVDD to 2D5V_S3
7>Modify core voltage setting: (1)R313:100K->Dummy (2)R311:Dummy->1K (3)R325,R326:1K->Dummy (4)R328,R329:Dummy->100K
8>Modify GPIO of KBC: (1)P20:HOTKEY->CHG_FLASH (2)P66:PCB_VER_SET2->EN_FLASH
9>R403:33R(63.33034.1D1)->0R(63.R0034.1D1)
10>Add U86 to modify the driving voltage from 3.3V to 5V
11>VGAU34: 71.00722.00U->71.00722.A0U
* SB - > SC:
Page 3:
1> Reserve test pads for 48MSEL100/66# and DIV4#
2> Change R418 to 0R and BC351 to dummy to tune 48M signal quality
Page 7:
3> Change
GPIO2 to MP_COMMAND, GPIO3 to MP_ACK, GPIO6 to OBLAN-80211#, GPIO20 to AD_OFF, GPIO29 to PCI_REQ#3, GPIO30 to PCI_GNT#3
Page 11:
4> Modify the logic of STD_LED and PWR_LED
5> Add R521 to pull 3D3V_S0 for SUSB#
Page 12:
6> Change R269 pull H plane from 5V_S0 to 3D3V_S0
Page 13:
7> Change HDD connecter for ME request
8> Add pull H for PCI_REQ#3, PCI_GNT#3. and PCI_PERR#
Page 14:
9> Change PCI_REQ# from 1 to 3 , PCI_GNT# from 1 to 3
10> Add R546 between BAN_PME# and CARDBUS_PME#
Page 15:
11> Change the cardbus socket SKT3 for ME request
Page 16:
12> Change PLLVDD(Pin 1) to 3D3V_S0
13> Dummy Pin121~125 for 43AB21, but reserve resisters for 43AB22
Page 17/18:
14> Mount the components for RTL8100BL
15> Add R524 and Q32 for preventing leakage current
16> Modify JK2(RJ11-45) for ME request
17> Add circuit for BIOS setting between LAN and 802.11
Page 19:
18> Add BC486 and BC488 for EMI request
Page 20/21/22:
19> Add BEEP from uP to control BEEP sound
20> Codec Pin 27: NC
21> Add BC487 between AUD_GND and DIG_GND for EMI
22> Change U75 and U80 to GMT 1211
23> Change U77 to APA2020
24> Performance tuing:
(1) BC308 to 0.01UF (2)BC466, BC467, and BC469 to 3.3V (3)R491 to 470R (4)DUMMY:BC424, BC448, BC451, R506, R381,
R383, BC475, BC476, BC434, BC432 (5)Change R513, R516, R497, R495 to 12K(6)Change R514, R496 to 15K (7)R498, R515 to
27K (8)R382, R380 to 0R3
Page 23:
25> Modify KBC P27 to NC, P40 to EMAIL_LED#, P65 to BACKLIGHT_OFF#
Page 24:
26> Change button_interrupt from IRQ7 to PCI_INTB#
Page 28:
27> Reserve R532 for EMI request
28> Add R531to pull L(Reduce_on)
Page 29:
29> Change U3 and U36 to FDS6982S, then dummy D3 and D17
30> Change D13 and D14 to 83.1R003.A8F
Page 32:
U9 -pin 13: NC
Page 33:
31> Modify the U48 circuit for preventing U48(5V) drive 82440MX(3V)
32> Use U48 to replace U9(uP) to contorl charge_LED
Page 34:
33> Reserve test pads for clock-down circuit
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
TM100 Rev_History
Size
Document Number
Rev
C
TM100
-1
Date:
Thursday, April 04, 2002
Sheet
2
of
35
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Clock Generator
CPU CLOCK = 440BX CLOCK + 877 MILS
440BX CLOCK = 1.25 ~ 1.35 inches
SA->SB
R403 0R2-0
63.R0034.1D1
3D3V_S0
2
1
6
14MGCL_D3
2D5V_S0
R405 33R2
63.33034.1D1
CLK_3D3V_S0
CLK_3D3V_S0
2
1
7
14M_P4
SB->SC
R419
10KR2
63.10334.1D1
R412
10KR2
63.10334.1D1
R411
10KR2
63.10334.1D1
R417
10KR2
63.10334.1D1
R402
DUMMY-R2
R404 33R2
63.33034.1D1
TP32
U65
1
2
14MP4
14M_IN
PCLKMX
1
28
R400 33R2
63.33034.1D1
48MSEL100/66#
7
PCLK_MX
REF0
VDDREF
2
27
14MVGA
1
2
XTAL_IN
REF1
14M_VGA 9
14M_OUT
CPU_STOP#1
3
26
SPREAD#
XTAL_OUT
SPREAD#
4
25
R413 22R2
63.22034.1D1
TP33
R4 2 1 33R2
63.33034.1D1
PCICLK_F
VDDCPU
1
2
PCLKVGA
5
24
CLKCPUCLK0
1
2
DIV4#
9
PCLK_VGA
CLK_CPUCLK0 4,7
PCICLK1
CPUCLK0
PCLKPCM
6
23
PCICLK2
CPUCLK1
7
22
VSSPCI
VSSCPU
R420 33R2
63.33034.1D1
8
21
D31 DUMMY-S1N4148
ZZ.04148.011
VDDPCI
VSSCORE
1 2
R424 33R2
63.33034.1D1
PCLKLAN
9
20
SUSA#
2
1
CLK_PWRDN#
14
PCLK_PCM
PCICLK3
PCI_STOP#
CLK_PCI_STOP# 7
CC_CPUSTP# 6,27
7
SUSA#
63.R0034.1D1
1
PCLKMINI
PCLK1394
10
19
PCICLK4
VDDCORE
11
18
CPU_STOP#1
R415
0R2-0
2
PCICLK5
CPU_STOP#
1 2
R423 33R2
63.33034.1D1
12
17
CLK_PWRDN#
17
PCLK_LAN
EPCICLK
PWRDWN#
SPREAD#
13
16
DIV4#
1
2
VDD
DIV4#
48MSEL100/66#
14
15
USBCLK/SEL100/66#
VSS48
1
2
R414
DUMMY-R2
ZZ.DUMMY.X02
19
PCLK_MINI
ICS9248-61
R401
10KR2
63.10334.1D1
R422 33R2
63.33034.1D1
1
2
16
PCLK_1394
R418 0R2-0
63.R0034.1D1
SB->SC
1
2
7
48M_P4
R444 10R2
63.10034.1D1
1
2
25
SIO_48M
BC351
DUMMY-SC10P
ZZ.10034.1B1
3D3V_S0
SB->SC
CLK_3D3V_S0
*Layout*
20 mil
BC333
2D5V_S0
R442
0R3-0-U
1
2
14M_IN
3D3V_S0
1
2
DUMMY-C3
BC330
SC4D7U10V5ZY
78.47593.411
X3
X-14.318MHZ-1
BC350
SCD1U
78.10492.4B1
BC339
SCD1U
78.10492.4B1
BC340
SCD1U
78.10492.4B1
BC331
SCD1U
78.10492.4B1
BC329
SCD1U
78.10492.4 B1
BC338
SC4D7U10V5ZY
78.47593.411
3D3V_S0 6,7,8,11,12,13,14,15,16,17,19,20,23,24,25,26,27,28,30,35
BC332
2D5V_S0
1
2
14M_OUT
(PIN 28)
near Chip Pin
(PIN 25)
(PIN 8)
(PIN 13)
(PIN 19)
DUMMY-C3
2D5V_S0 4,28
SDRAM Clock Buffer
3D3V_S0
BC80
SCD1U
78.10492.4B1
BC83
SCD1U
78.10492.4B1
BC85
SCD1U
78.10492.4B1
BC81
SC4D7U10V5ZY
7 8.47593.411
*Layout*
DCLKIN longer than other
CLK (2.4inch)
3D3V_S0
3D3V_S0
PLL
SHUTDOWN
OUTPUT
SOURCE
FS2
FS1
CLKA[1..4]
CLKB[1..4]
CLKOUT
TRISTATE
TRISTATE
DRIVEN
PLL
N
0
0
R108
DUMMY-R2
ZZ.DUMMY.X02
R119
1KR2
63.10234.1D1
3D3V_S0
0
1
DRIVEN
TRISTATE
DRIVEN
PLL
N
*1
0
REF
Y
DRIVEN
DRIVEN
DRIVEN
U13
R114 22R2
63.22034.1D1
DRIVEN
DRIVEN
DRIVEN
PLL
N
1
1
1
16
DCLKIN_R
2
1
7
CLKDBUF
REF
CLKOUT
DCLKIN
7
R121 10R2
63.10034.1D1
R116 10R2
63.10034.1D1
2
15
CLKA1
CLKA4
1
2
3
14
1
2
SDRAMCK1
SDRAMCK3
8
CLK_SDRAM1
CLK_SDRAM3 8
CLKA2
CLKA3
4
13
VDD
VDD
R122 10R2
63.10034.1D1
R115 10R2
63.10034.1D1
5
12
GND
GND
1
2
6
11
1
2
SDRAMCK0
SDRAMCK2
8
CLK_SDRAM0
CLK_SDRAM2 8
CLKB1
CLKB4
7
10
CLKB2
CLKB3
R125
56R3
63.56034.151
8
9
FS2
FS1
ICS9112BM-17
R120
DUMMY-R2
ZZ.DUMMY.X02
BC82
DUMMY-C3
R123
100KR2
63.10434.1D1
R124
100KR2
63.10434.1D1
R107
1KR2
63.10234.1D1
R118
100KR2
63.10434.1D1
R117
100KR2
63.10434.1D1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
BC84
SC15P
78.15034.1B1
Title
Clock Generator & SDRAM Clock Buffer
Size
Document Number
Rev
A3
TM100
-1
Date:
Thursday, April 04, 2002
S heet
3
of
35
908697647.653.png 908697647.665.png 908697647.676.png 908697647.687.png 908697647.698.png 908697647.709.png 908697647.720.png 908697647.731.png 908697647.742.png 908697647.753.png 908697647.764.png 908697647.776.png 908697647.787.png 908697647.798.png 908697647.809.png 908697647.820.png 908697647.831.png 908697647.842.png 908697647.853.png 908697647.864.png 908697647.875.png 908697647.887.png 908697647.898.png 908697647.909.png 908697647.920.png 908697647.931.png 908697647.942.png 908697647.953.png 908697647.964.png 908697647.975.png 908697647.986.png 908697647.998.png 908697647.1009.png 908697647.1020.png 908697647.1031.png 908697647.1042.png 908697647.1053.png 908697647.1064.png 908697647.1075.png 908697647.1086.png 908697647.1097.png 908697647.1109.png 908697647.1120.png 908697647.1131.png 908697647.1142.png 908697647.1153.png 908697647.1164.png 908697647.1175.png 908697647.1186.png 908697647.1197.png 908697647.1208.png 908697647.1220.png 908697647.1231.png 908697647.1242.png 908697647.1253.png 908697647.1264.png 908697647.1275.png 908697647.1286.png 908697647.1297.png 908697647.1308.png 908697647.1319.png 908697647.1331.png 908697647.1342.png 908697647.1353.png 908697647.1364.png 908697647.1375.png 908697647.1386.png 908697647.1397.png 908697647.1408.png 908697647.1419.png 908697647.1430.png 908697647.1442.png 908697647.1453.png 908697647.1464.png 908697647.1475.png 908697647.1486.png 908697647.1497.png 908697647.1508.png 908697647.1519.png 908697647.1530.png 908697647.1541.png 908697647.1553.png 908697647.1564.png 908697647.1575.png 908697647.1586.png 908697647.1597.png 908697647.1608.png 908697647.1619.png 908697647.1630.png 908697647.1641.png 908697647.1652.png 908697647.1664.png 908697647.1675.png 908697647.1686.png 908697647.1697.png 908697647.1708.png 908697647.1719.png 908697647.1730.png 908697647.1741.png 908697647.1752.png 908697647.1763.png 908697647.1775.png 908697647.1786.png 908697647.1791.png 908697647.1792.png 908697647.1793.png 908697647.1794.png 908697647.1795.png 908697647.1796.png 908697647.1797.png 908697647.1798.png 908697647.1800.png 908697647.1801.png 908697647.1802.png 908697647.1803.png 908697647.1804.png 908697647.1805.png 908697647.1806.png 908697647.1807.png 908697647.1808.png 908697647.1809.png 908697647.1811.png 908697647.1812.png 908697647.1813.png 908697647.1814.png 908697647.1815.png 908697647.1816.png 908697647.1817.png 908697647.1818.png 908697647.1819.png 908697647.1820.png 908697647.1822.png 908697647.1823.png 908697647.1824.png 908697647.1825.png 908697647.1826.png 908697647.1827.png 908697647.1828.png 908697647.1829.png 908697647.1830.png 908697647.1831.png 908697647.1833.png 908697647.1834.png 908697647.1835.png 908697647.1836.png 908697647.1837.png 908697647.1838.png 908697647.1839.png 908697647.1840.png 908697647.1841.png 908697647.1842.png 908697647.1844.png 908697647.1845.png 908697647.1846.png 908697647.1847.png 908697647.1848.png 908697647.1849.png 908697647.1850.png 908697647.1851.png 908697647.1852.png 908697647.1853.png 908697647.1855.png 908697647.1856.png 908697647.1857.png 908697647.1858.png 908697647.1859.png 908697647.1860.png 908697647.1861.png 908697647.1862.png 908697647.1863.png 908697647.1864.png 908697647.1866.png 908697647.1867.png 908697647.1868.png 908697647.1869.png 908697647.1870.png 908697647.1871.png 908697647.1872.png 908697647.1873.png 908697647.1874.png 908697647.1875.png 908697647.1877.png 908697647.1878.png 908697647.1879.png 908697647.1880.png 908697647.1881.png 908697647.1882.png 908697647.1883.png 908697647.1884.png 908697647.1885.png 908697647.1886.png 908697647.1888.png 908697647.1889.png 908697647.1890.png 908697647.1891.png 908697647.1892.png 908697647.1893.png 908697647.1894.png 908697647.1895.png 908697647.1896.png 908697647.1897.png 908697647.1899.png 908697647.1900.png 908697647.1901.png 908697647.1902.png 908697647.1903.png 908697647.1904.png 908697647.1905.png 908697647.1906.png 908697647.1907.png 908697647.1908.png 908697647.1910.png 908697647.1911.png 908697647.1912.png 908697647.1913.png 908697647.1914.png 908697647.1915.png 908697647.1916.png 908697647.1917.png 908697647.1918.png 908697647.1919.png 908697647.1921.png 908697647.1922.png 908697647.1923.png 908697647.1924.png 908697647.1925.png 908697647.1926.png 908697647.1927.png 908697647.1928.png 908697647.1929.png 908697647.1930.png 908697647.1932.png 908697647.1933.png 908697647.1934.png 908697647.1935.png 908697647.1936.png 908697647.1937.png 908697647.1938.png 908697647.1939.png 908697647.1940.png 908697647.1941.png 908697647.1943.png 908697647.1944.png 908697647.1945.png 908697647.1946.png 908697647.1947.png 908697647.1948.png 908697647.1949.png 908697647.1950.png 908697647.1951.png 908697647.1952.png 908697647.1954.png 908697647.1955.png 908697647.1956.png 908697647.1957.png 908697647.1958.png 908697647.1959.png 908697647.1960.png 908697647.1961.png 908697647.1962.png 908697647.1963.png 908697647.1965.png 908697647.1966.png 908697647.1967.png 908697647.1968.png 908697647.1969.png 908697647.1970.png 908697647.1971.png 908697647.1972.png 908697647.1973.png 908697647.1974.png 908697647.1976.png 908697647.1977.png 908697647.1978.png 908697647.1979.png 908697647.1980.png 908697647.1981.png 908697647.1982.png 908697647.1983.png 908697647.1984.png 908697647.1985.png 908697647.1987.png 908697647.1988.png 908697647.1989.png 908697647.1990.png 908697647.1991.png 908697647.1992.png 908697647.1993.png 908697647.1994.png 908697647.1995.png 908697647.1996.png 908697647.1998.png 908697647.1999.png 908697647.2000.png 908697647.2001.png 908697647.2002.png 908697647.2003.png 908697647.2004.png 908697647.2005.png 908697647.2006.png 908697647.2007.png 908697647.2009.png 908697647.2010.png 908697647.2011.png 908697647.2012.png 908697647.2013.png 908697647.2014.png 908697647.2015.png 908697647.2016.png 908697647.2017.png 908697647.2018.png 908697647.2020.png 908697647.2021.png 908697647.2022.png 908697647.2023.png 908697647.2024.png 908697647.2025.png 908697647.2026.png 908697647.2027.png 908697647.2028.png 908697647.2029.png 908697647.2031.png 908697647.2032.png 908697647.2033.png 908697647.2034.png 908697647.2035.png 908697647.2036.png 908697647.2037.png 908697647.2038.png 908697647.2039.png 908697647.2040.png 908697647.2042.png 908697647.2043.png 908697647.2044.png 908697647.2045.png 908697647.2046.png 908697647.2047.png 908697647.2048.png 908697647.2049.png 908697647.2050.png 908697647.2051.png 908697647.2053.png 908697647.2054.png 908697647.2055.png 908697647.2056.png 908697647.2057.png 908697647.2058.png 908697647.2059.png 908697647.2060.png 908697647.2061.png 908697647.2062.png 908697647.2064.png 908697647.2065.png 908697647.2066.png 908697647.2067.png 908697647.2068.png 908697647.2069.png 908697647.2070.png 908697647.2071.png 908697647.2072.png 908697647.2073.png 908697647.2075.png 908697647.2076.png 908697647.2077.png 908697647.2078.png 908697647.2079.png 908697647.2080.png 908697647.2081.png 908697647.2082.png 908697647.2083.png 908697647.2084.png 908697647.2086.png 908697647.2087.png 908697647.2088.png 908697647.2089.png 908697647.2090.png 908697647.2091.png 908697647.2092.png 908697647.2093.png 908697647.2094.png 908697647.2095.png 908697647.2097.png 908697647.2098.png 908697647.2099.png 908697647.2100.png 908697647.2101.png 908697647.2102.png 908697647.2103.png 908697647.2104.png 908697647.2105.png 908697647.2106.png 908697647.2108.png 908697647.2109.png 908697647.2110.png 908697647.2111.png 908697647.2112.png 908697647.2113.png 908697647.2114.png 908697647.2115.png 908697647.2116.png 908697647.2117.png 908697647.2119.png 908697647.2120.png 908697647.2121.png 908697647.2122.png 908697647.2123.png 908697647.2124.png 908697647.2125.png 908697647.2126.png 908697647.2127.png 908697647.2128.png 908697647.2130.png 908697647.2131.png 908697647.2132.png 908697647.2133.png 908697647.2134.png 908697647.2135.png 908697647.2136.png 908697647.2137.png 908697647.2138.png 908697647.2139.png 908697647.2141.png 908697647.2142.png 908697647.2143.png 908697647.2144.png 908697647.2145.png 908697647.2146.png 908697647.2147.png 908697647.2148.png 908697647.2149.png 908697647.2150.png 908697647.2152.png 908697647.2153.png 908697647.2154.png 908697647.2155.png 908697647.2156.png 908697647.2157.png 908697647.2158.png 908697647.2159.png 908697647.2160.png 908697647.2161.png 908697647.2164.png 908697647.2165.png 908697647.2166.png 908697647.2167.png 908697647.2168.png 908697647.2169.png 908697647.2170.png 908697647.2171.png 908697647.2172.png 908697647.2173.png 908697647.2175.png 908697647.2176.png 908697647.2177.png 908697647.2178.png 908697647.2179.png 908697647.2180.png 908697647.2181.png 908697647.2182.png 908697647.2183.png 908697647.2184.png 908697647.2186.png 908697647.2187.png 908697647.2188.png
 
VCC_CORE_S0
VCCT_S0
VCCT_S0
1D5V_S0
5,27
VCC_CORE_S0
5,28
1D5V_S0
VCCT_S0
R191
200R3
R251
150R3
R297
200R3
BC145
SCD1U
78.10492.4B1
5,6,7,28
VCCT_S0
VCC_CORE_S0
TP28
TPAD30
ZZ.PAD30.XXX
TP21
TPAD30
TP15
TPAD30
TP14
TPAD30
TP13
TPAD30
ITP_TDI
R174
56D2R3F
64.56R25.651
U5A
U5B
ITP_TDO
AD19
D22
CPU_PICD0
7
GTL_HA#[31..3]
GTL_HD#[63..0] 7
PICD0
VCC_0
GTL_HA#3
K1
A16
GTL_HD#0
CPU_PICD1
AD17
F22
A3#
D0#
PICD1
VCC_1
GTL_HA#4
ITP_TRST#
J1
B17
GTL_HD#1
CPU_PICCLK
AF20
E21
A4#
D1#
PICCLK
VCC_2
GTL_HA#5
G2
A17
R185
1KR3
63.10234.151
H22
GTL_HD#2
A5#
D2#
VCC_3
GTL_HA#6
K3
D23
GTL_HD#3
R186
1KR3
63.10234.151
R175
1KR3
63.10234.151
AF22
G21
A6#
D3#
BP2#
VCC_4
GTL_HA#7
ITP_PREQ#
J2
B19
GTL_HD#4
AE20
K22
A7#
D4#
BP3#
VCC_5
GTL_HA#8
GTL_HA#10
H3
C20
AD22
J21
GTL_HD#5
A8#
D5#
BPM0#
VCC_6
R173
GTL_HA#9
G1
C16
GTL_HD#6
AD21
M22
A9#
D6#
BPM1#
VCC_7
ITP_PRDY#_TP
1
2
ITP_PRDY#
A3
A20
GTL_HD#7
L21
A10#
D7#
VCC_8
GTL_HA#11
J3
A22
GTL_HD#8
ITP_TCK
AD10
P22
A11#
D8#
TCK
VCC_9
240R3
GTL_HA#12
H1
A19
GTL_HD#9
ITP_TDI
AD7
N21
A12#
D9#
TDI
VCC_10
GTL_HA#13
D3
A23
GTL_HD#10
ITP_TDO
AD11
T22
A13#
D10#
TDO
VCC_11
R192
510R3
GTL_HA#14
F3
A24
GTL_HD#11
ITP_TMS
AF7
R21
A14#
D11#
TMS
VCC_12
GTL_HA#15
G3
C18
GTL_HD#12
ITP_TRST#
ITP_PREQ#
AF15
V22
A15#
D12#
TRST#
VCC_13
GTL_HA#16
C2
D24
GTL_HD#13
AF19
U21
A16#
D13#
PREQ#
VCC_14
GTL_HA#17
B5
B24
GTL_HD#14
ITP_PRDY#
AE22
Y22
A17#
D14#
PRDY#
VCC_15
GTL_HA#18
B11
A18
GTL_HD#15
W21
A18#
D15#
VCC_16
GTL_HA#19
C6
E23
GTL_HD#16
AF12
AB22
A19#
D16#
5
CPU_CMOSREF
CMOSREF_1
VCC_17
GTL_HA#20
B9
B21
GTL_HD#17
AD5
AA21
A20#
D17#
CMOSREF_0
VCC_18
GTL_HA#21
B7
B23
GTL_HD#18
R188
AC21
A21#
D18#
VCC_19
GTL_HA#22
C8
E26
GTL_HD#19
1
2
CPU_RTTIMPEDP
AE16
D20
A22#
D19#
RTTIMPEDP
VCC_20
1D5V_S0
GTL_HA#23
A8
C24
GTL_HD#20
F20
A23#
D20#
VCC_21
GTL_HA#24
A10
F24
GTL_HD#21
56D2R3F
64.56R25.651
L5
E19
A24#
D21#
6
CC_PERF#
GHI#
VCC_22
R249 3KR3
63.30234.151
1 2
R187 1KR3
63.10234.151
GTL_HA#25
B3
D25
GTL_HD#22
AB20
A25#
D22#
VCC_23
CC_FLUSH#
GTL_HA#26
GTL_HD#23
GHI#:internal pull
up to VCCT
A13
E24
AF21
AA19
A26#
D23#
5,7
AGTLREF
VREF_1
VCC_24
GTL_HA#27
A9
B25
GTL_HD#24
AB26
AC19
A27#
D24#
VREF_2
VCC_25
GTL_HA#28
GTL_HA#29
C3
G24
GTL_HD#25
H26
D18
A28#
D25#
VREF_3
VCC_26
GTL_HD#26
CC_INIT#
1 2
R246 680R3
63.68134.151
C12
H24
A21
F18
A29#
D26#
VREF_4
VCC_27
GTL_HA#30
C10
F26
GTL_HD#27
VCCT_S0
VCC_CORE_S0
AF9
E17
A30#
D27#
VREF_5
VCC_28
GTL_HA#31
A6
L24
GTL_HD#28
R127
A4
AB18
A31#
D28#
VREF_6
VCC_29
CC_STPCLK#
GTL_HD#29
1
2
A15
H25
1
2
N1
AA17
A32#
D29#
VREF_7
VCC_30
A14
C26
GTL_HD#30
AA1
AC17
A33#
D30#
VREF_8
VCC_31
1D5V_S0
B13
K24
GTL_HD#31
R290
0R3-0-U
63.R0004.151
1KR3
D16
A34#
D31#
VCC_32
A12
G26
GTL_HD#32
CPU_TESTLO_1
Y4
F16
A35#
D32#
TESTLO
VCC_33
GTL_HD#33
RN6
K25
R5
E15
7
GTL_REQ#[0..4]
D33#
VCC
VCC_34
CC_INTR
CC_NMI
CC_DPSLP#
1
2
3
4
8
GTL_REQ#0
GTL_REQ#1
R1
J24
GTL_HD#34
AB16
L 11
REQ0#
D34#
VCC_35
7
L3
CPU
1/4
K26
GTL_HD#35
CPU_PLL
1
2
CPU_PLL1
CPU_PLL2
N3
CPU
AA15
REQ1#
D35#
PLL1
VCC_36
GTL_REQ#2
GTL_REQ#4
GTL_HD#36
2D5V_S0
6
T1
F25
N2
AC15
REQ2#
D36#
PLL2
VCC_37
CC_SMI#
5
GTL_REQ#3
U1
N26
GTL_HD#37
IND-4D7UH
D14
REQ3#
D37#
VCC_38
L1
J26
GTL_HD#38
TC7
SE33U8V-U
79.3361U.9P1
P1
F14
REQ4#
D38#
NC
VCC_39
SRN1K5-1
66.15236.08A
GTL_HD#39
M24
P5
E13
D39#
NC
VCC_40
1D5V_S0
T4
U26
GTL_HD#40
R293
1KR3F
64.10015.651
E1
2/4
AB14
RP#
D40#
NC
VCC_41
AA3
P25
GTL_HD#41
CPUCLKREF
F1
AA13
7
GTL_ADS#
ADS#
D41#
NC
VCC_42
GTL_HD#42
RN3
L26
AC13
D42#
VCC_43
CC_A20M#
CC_FERR#
CC_IERR#
CC_IGNNE#
1
2
3
4
8
W2
R24
GTL_HD#43
AC1
D12
3,7
CLK_CPUCLK0
AERR#
D43#
CLK0
VCC_44
7
AB3
R26
GTL_HD#44
AD1
F12
AP0#
D44#
BLK0#/CLKREF
VCC_45
GTL_HD#45
R126
6
P3
M25
E11
AP1#
D45#
VCC_46
5
FOR NOISE
REDUCTION
C14
V25
GTL_HD#46
2
1
CPU_TESTLO
M1
AB12
BERR#
D46#
TESTLO
VCC_47
AF23
T24
GTL_HD#47
R291
1KR3F
64.10015.651
AA11
BINIT#
D47#
VCC_48
CC_IERR#
GTL_HD#48
BC258
SC1U10V3ZY
78.10593.4B1
1KR3
SRN1K5-1
66.15236.08A
AF4
M26
AF18
AC11
IERR#
D48#
NC
VCC_49
P24
AD16
D10
GTL_HD#49
D49#
NCHCTRLP
VCC_50
A7
AA26
GTL_HD#50
VCCT_S0
AF11
F10
7
GTL_BREQ#0
BREQ0#
D50#
TESTHI
VCC_51
GTL_HD#51
R189
C4
T26
AE8
E9
NC
D51#
NC
VCC_52
C22
U24
GTL_HD#52
1
2
AB10
CPU_NCHCTRLP
NC
D52#
VCC_53
AD23
Y25
GTL_HD#53
AA9
NC
D53#
VCC_54
2D5V_S0
GTL_HD#54
14R3F
R2
W26
N24
AC9
7
GTL_BPRI#
BPRI#
D54#
NC
VCC_55
L2
V26
GTL_HD#55
Place near CPU
D8
7
GTL_BNR#
BNR#
D55#
VCC_56
V3
AB25
GTL_HD#56
R252
AE10
F8
7
GTL_LOCK#
LOCK#
D56#
NC
VCC_57
1D8V_S0
GTL_HD#57
T25
1
2
CPU_TESTHI_1
E2
E7
D57#
TESTHI
VCC_58
R295
1KR3F
64.10015.651
GTL_HD#58
AA2
Y24
AB8
7
GTL_HIT#
HIT#
D58#
VCC_59
U2
W24
GTL_HD#59
1KR3
P4
AA7
7
GTL_HITM#
HITM#
D59#
NC
VCC_61
T3
Y26
GTL_HD#60
R286
AC7
7
GTL_DEFER#
DEFER#
D60#
VCC_62
GTL_HD#61
AB24
1
2
CPU_TESTHI
AB6
D6
D61#
VCC_76
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Y3
AA24
GTL_HD#62
AA5
F6
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GTL_RS#0
RS0#
D62#
VCC_77
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V1
V24
GTL_HD#63
1KR3
AC5
E5
7
GTL_RS#1
RS1#
D63#
VCC_78
VCC_65
1D8V_S0
U3
M6
H6
7
GTL_TRDY#
GTL_RS#2
RS2#
VCC_79
VCC_66
R292
2K49R3F
64.24915.651
M5
AE24
P6
G5
RSP#
DEP0#
VCC_80
VCC_67
BC257
SCD1U
78.10492.4B1
W1
AD25
VCC_CORE_S0
W5
K6
7
TRDY#
DEP1#
VCC_75
VCC_68
AE25
Y6
J5
DEP2#
VCC_74
VCC_69
R294
1K5R3
63.15234.151
AC3
AC24
U5
N5
7
CC_A20M#
A20M#
DEP3#
VCC_73
VCC_70
CC_FERR#
CC_FLUSH#
AF6
AF24
VCCT_S0
V6
T6
7
CC_FERR#
FERR#
DEP4#
VCC_72
VCC_71
AF5
AD26
FLUSH#
DEP5#
AD9
AC26
7
CC_IGNNE#
IGNNE#
DEP6#
AD3
AD24
6
CC_SMI#
SMI#
DEP7#
TUAL700
71.TULAT.G0U
R250
39R3
CC_CPUPWRGD
AB4
6
CC_CPUPWRGD
PWRGOOD
W3
GTL_DBSY# 7
DBSY#
VCCT_S0
Y1
71.TULAT.G0U(700MHz)
DRDY#
GTL_DRDY# 7
AE4
6
CC_STPCLK#
STPCLK#
AF8
AF13
THERMDP1 12
27
CC_DPSLP#
DPSLP#
THERMDA
AF14
ITP_TMS
TP22
TPAD30
THERMDN 12
THERMDC
R245
56D2R3F
64.56R25.651
AD15
6
CC_INTR
INTR/LINT0
AE14
AE12
TP3
TPAD30
ZZ.PAD30.XXX
H_BSEL0_3D3
H_BSEL1_3D3
6
CC_NMI
NMI/LINT1
SELFSB0
AF10
TP2
TPAD30
ZZ.PAD30.XXX
ITP_TCK
TP23
TPAD30
SELFSB1
R243
AE6
R 253
6
CC_INIT#
INIT#
GTL_CPURST1#
1
2
B15
AF16
CPU_EDGCTRLP
2
1
6,7
GTL_CPURST#
RESET#
EDGECTRLP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
0R3-0-U
63.R0004.151
39R3
R190
110R3F
R244
TUAL700
71.TULAT.G0U
Layout note:
Place CPU_RST# Resistor < 0.1" from CPU
GTL_CPURST#
1
2
CG_CPURST#_TP
TP20
TPAD30
Title
240R3
CPU 1/2
Size
Document Number
Rev
A3
TM100
-1
Date:
Thursday, April 04, 2002
S heet
4
of
35
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908697647.415.png 908697647.416.png 908697647.417.png 908697647.418.png 908697647.419.png 908697647.420.png 908697647.421.png 908697647.422.png 908697647.423.png 908697647.424.png 908697647.425.png 908697647.426.png 908697647.427.png 908697647.428.png 908697647.429.png 908697647.430.png 908697647.431.png 908697647.432.png 908697647.434.png 908697647.435.png 908697647.436.png 908697647.437.png 908697647.438.png 908697647.439.png 908697647.440.png 908697647.441.png 908697647.442.png 908697647.443.png 908697647.446.png 908697647.447.png 908697647.448.png 908697647.449.png 908697647.450.png 908697647.451.png 908697647.452.png 908697647.453.png 908697647.454.png 908697647.455.png 908697647.457.png 908697647.458.png 908697647.459.png 908697647.460.png 908697647.461.png 908697647.462.png 908697647.463.png 908697647.464.png 908697647.465.png 908697647.466.png 908697647.468.png 908697647.469.png 908697647.470.png 908697647.471.png 908697647.472.png 908697647.473.png 908697647.474.png 908697647.475.png 908697647.476.png 908697647.477.png 908697647.479.png 908697647.480.png 908697647.481.png 908697647.482.png 908697647.483.png 908697647.484.png 908697647.485.png 908697647.486.png 908697647.487.png 908697647.488.png 908697647.490.png 908697647.491.png 908697647.492.png 908697647.493.png 908697647.494.png 908697647.495.png 908697647.496.png 908697647.497.png 908697647.498.png 908697647.499.png 908697647.501.png 908697647.502.png 908697647.503.png 908697647.504.png 908697647.505.png 908697647.506.png 908697647.507.png 908697647.508.png 908697647.509.png 908697647.510.png 908697647.512.png 908697647.513.png 908697647.514.png 908697647.515.png 908697647.516.png 908697647.517.png 908697647.518.png 908697647.519.png 908697647.520.png 908697647.521.png 908697647.523.png 908697647.524.png 908697647.525.png 908697647.526.png 908697647.527.png 908697647.528.png 908697647.529.png 908697647.530.png 908697647.531.png 908697647.532.png 908697647.534.png 908697647.535.png 908697647.536.png 908697647.537.png 908697647.538.png 908697647.539.png 908697647.540.png 908697647.541.png 908697647.542.png 908697647.543.png 908697647.545.png 908697647.546.png 908697647.547.png 908697647.548.png 908697647.549.png 908697647.550.png 908697647.551.png 908697647.552.png 908697647.553.png 908697647.554.png 908697647.557.png 908697647.558.png 908697647.559.png 908697647.560.png 908697647.561.png 908697647.562.png 908697647.563.png 908697647.564.png 908697647.565.png 908697647.566.png 908697647.568.png 908697647.569.png 908697647.570.png 908697647.571.png 908697647.572.png 908697647.573.png 908697647.574.png 908697647.575.png 908697647.576.png 908697647.577.png 908697647.579.png 908697647.580.png 908697647.581.png 908697647.582.png 908697647.583.png 908697647.584.png 908697647.585.png 908697647.586.png 908697647.587.png 908697647.588.png 908697647.590.png 908697647.591.png 908697647.592.png 908697647.593.png 908697647.594.png 908697647.595.png 908697647.596.png 908697647.597.png 908697647.598.png 908697647.599.png 908697647.601.png 908697647.602.png
 
U5C
VCCT_S0
U5D
E16
F19
VSS_0
VSS_142
R4
E20
VSS_1
VSS_141
E25
C25
A26
AD4
VSS_2
VSS_140
VCCT_1
NC_1
G25
A25
G23
A5
VSS_3
VSS_139
VCCT_2
NC_2
J25
AE1
J23
D1
VSS_4
VSS_138
VCCT_3
NC_3
L25
AD2
BC215
SC1U10V3ZY
78.10593.4B1
BC168
SC1U10V3ZY
BC205
SC1U10V3ZY
BC261
SC1U10V3ZY
BC148
SC1U10V3ZY
L23
AD13
VSS_5
VSS_137
VCCT_4
NC_4
N25
AB2
N23
B1
VSS_6
VSS_136
VCCT_5
NC_5
R25
Y2
R23
P26
VSS_7
VSS_135
VCCT_6
NC_6
U25
V2
U23
A11
VSS_8
VSS_134
VCCT_7
NC_7
W25
T2
W23
A2
VCCT_S0
VSS_9
VSS_133
VCCT_8
NC
AA25
P2
AA23
VSS_10
VSS_132
VCCT_9
AC25
M2
C21
AE18
VSS_11
VSS_131
VCCT_10
VCCT_36
AF25
K2
C19
VSS_12
VSS_130
VCCT_11
AE26
H2
AD20
VSS_13
VSS_129
VCCT_12
C23
F2
BC147
SC1U10V3ZY
BC184
SC1U10V3ZY
BC259
SC1U10V3ZY
BC256
SC1U10V3ZY
BC183
SC1U10V3ZY
C17
VSS_14
VSS_128
VCCT_13
F23
D2
AD18
CPU
4/4
AB1
VSS_15
VSS_127
VCCT_14
VID0
CPU_VID0
27
H23
B2
C15
AC2
VSS_16
VSS_126
VCCT_15
VID1
CPU_VID1
27
K23
W4
C13
AE2
CPU_VID2
27
VSS_17
VSS_125
VCCT_16
VID2
M23
U4
AD14
AF3
CPU_VID3
27
VSS_18
VSS_124
VCCT_17
VID3
P23
M3
C11
R3
VSS_19
VSS_123
VCCT_18
VID4
CPU_VID4
27
T23
K4
AD12
VSS_20
VSS_122
VCCT_19
V23
H4
C9
VSS_21
VSS_121
VCCT_20
Y23
F4
C7
VSS_22
VSS_120
VCCT_21
AB23
D4
AD8
B26
VSS_23
VSS_119
VCCT_22
VSS
AE23
B4
GTLREF( 2/3 +VCCT)
CMOSREF ( 2/3 1.5V )
C5
M4
VSS_24
VSS_118
VCCT_23
VSS
B22
AE5
AD6
AF26
VSS_25
VSS_117
VCCT_24
VSS
D21
AC6
AC23
VSS_26
VSS_116
VCCT_25
F21
AA6
AA4
VSS_27
VSS_115
VCCT_26
E22
AB5
VCCT_S0
1D5V_S0
E4
VSS_28
VSS_114
VCCT_27
H21
W6
G4
E3
VTTPWRGOOD_1D2
28
VSS_29
VSS_113
VCCT_28
VTTPWRGOOD
G22
Y5
J4
VSS_30
VSS_112
VCCT_29
K21
U6
L4
VSS_31
VSS_111
VCCT_30
J22
V5
AC4
D26
VSS_32
VSS_110
VCCT_31
NC
M21
R6
V4
VCCT_S0
VSS_33
VSS_109
VCCT_32
R289
1KR3F
Place resistors
between GMCH
and CPU
R247
1KR3F
L22
T5
AE3
VSS_34
VSS_108
VCCT_33
CPU
3/4
P21
L6
AF2
D5
VSS_35
VSS_107
VCCT_34
VCCT_37
N22
N6
AF1
E6
VSS_36
VSS_106
VCCT_35
VCCT_38
T21
J6
VSS_37
VSS_105
R22
K5
VSS_38
VSS_104
V21
G6
VSS_39
VSS_103
TUAL700
71.TULAT.G0U
U22
H5
4,7
AGTLREF
VSS_40
VSS_102
4
CPU_CMOSREF
Y21
F5
VSS_41
VSS_101
W22
B6
VSS_42
VSS_100
AB21
AE7
VSS_43
VSS_99
AA22
AC8
VSS_44
VSS_98
AC22
AA8
R288
2KR3F
BC255
SCD1U16V3KX
BC167
SCD1U16V3KX
BC149
SCD1U16V3KX
BC221
SCD1U16V3KX
R248
2KR3F
BC220
SCD1U16V3KX
BC219
SCD1U16V3KX
VSS_45
VSS_97
AE21
AB7
VSS_46
VSS_96
B20
E8
VSS_47
VSS_95
D19
F7
VSS_48
VSS_94
AB19
D7
VSS_49
VSS_93
AA20
B8
VSS_50
VSS_92
AC20
AE9
VSS_51
VSS_91
Place caps near CPU
AE19
AC10
VSS_52
VSS_90
B18
AA10
Place caps near CPU
VSS_53
VSS_89
D17
AB9
VSS_54
VSS_88
F17
E10
VSS_55
VSS_87
E18
F9
VSS_56
VSS_86
AB17
D9
VSS_57
VSS_85
AA18
B10
VSS_58
VSS_84
AC18
AE11
VSS_59
VSS_83
AE17
AC12
VSS_60
VSS_82
B16
AA12
VSS_61
VSS_81
D15
AB11
VCC_CORE_S0
VCC_CORE_S0
VSS_62
VSS_80
F15
E12
VSS_63
VSS_79
AB15
F11
VSS_64
VSS_78
AA16
D11
VSS_65
VSS_77
AC16
B12
VSS_66
VSS_76
AE15
AE13
BC174
SC10U10V-U
78.10613.2A1
BC212
SC10U10V-U
78.10613.2A1
BC210
SC10U10V-U
78.10613.2A1
BC176
SC10U10V-U
78.10613.2A1
BC180
SCD1U16V3KX
BC177
SCD1U16V3KX
BC179
SCD1U16V3KX
BC214
SCD1U16V3KX
VSS_67
VSS_75
B14
AC14
VSS_68
VSS_74
D13
AA14
VSS_69
VSS_73
F13
AB13
VSS_70
VSS_72
E14
VSS_71
C1
NC
VCC_CORE_S0
AF17
N4
NC
NC
TUAL700
71.TULAT.G0U
BC208
SCD1U16V3KX
BC175
SCD1U16V3KX
BC218
SCD1U16V3KX
BC206
SCD1U16V3KX
BC173
SCD1U16V3KX
BC217
SCD1U16V3KX
BC170
SCD1U16V3KX
BC178
SCD1U16V3KX
BC172
SCD1U16V3KX
BC171
SCD1U16V3KX
VCC_CORE_S0
4,27
VCC_CORE_S0
VCC_CORE_S0
VCCT_S0
4,6,7,28
VCCT_S0
BC182
SCD1U16V3KX
BC169
SCD1U16V3KX
BC146
SCD1U16V3KX
BC216
SCD1U16V3KX
BC207
SCD1U16V3KX
BC150
SCD1U16V3KX
BC213
SCD1U16V3KX
BC209
SCD1U16V3KX
BC181
SCD1U16V3KX
BC211
SCD1U16V3KX
1D5V_S0
4,28
1D5V_S0
Decouping Recommendation
0.47uF * 24
TM100
0.1uF * 24
Ver. 0.1
10uF / 6.3V * 12
Underneath balls
on solder side
On the peripheral
near balls
Use 2-3 vias per pad for reduced
inductance during layout
Placement should be near
processor for all
VCC_CORE
10uF / 6.3V * 10
10uF / 10V * 10
10uF / 6.3V * 10 + 6 * NS
Bulk Caps
220uF / 2.5V * 8
150uF / 4V * 12 + 2 * NS
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Place close to
processor for
all
1uF * 10
Use 2 vias per pad for reduced
inductance during layout
1uF * 10
1uF * 10 + 2 * NS
VCCT
Title
CPU 2/2 CONFIGURATION
Bulk Caps
220uF / 2.5V * 2
150uF / 4V * 5 + 1 * NS
Size
Document Number
Rev
Custom
TM100
-1
Almador-M Checklist Ver. 0.5 8/28
Date:
Thursday, April 04, 2002
Sheet
5
of
35
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908697647.662.png 908697647.663.png 908697647.666.png 908697647.667.png 908697647.668.png 908697647.669.png 908697647.670.png 908697647.671.png 908697647.672.png 908697647.673.png 908697647.674.png 908697647.675.png 908697647.677.png 908697647.678.png 908697647.679.png 908697647.680.png 908697647.681.png 908697647.682.png 908697647.683.png 908697647.684.png 908697647.685.png 908697647.686.png 908697647.688.png 908697647.689.png 908697647.690.png 908697647.691.png 908697647.692.png 908697647.693.png 908697647.694.png 908697647.695.png 908697647.696.png 908697647.697.png 908697647.699.png 908697647.700.png 908697647.701.png 908697647.702.png 908697647.703.png 908697647.704.png 908697647.705.png 908697647.706.png 908697647.707.png 908697647.708.png 908697647.710.png 908697647.711.png 908697647.712.png 908697647.713.png 908697647.714.png 908697647.715.png 908697647.716.png 908697647.717.png 908697647.718.png 908697647.719.png 908697647.721.png 908697647.722.png 908697647.723.png 908697647.724.png 908697647.725.png 908697647.726.png 908697647.727.png 908697647.728.png 908697647.729.png 908697647.730.png 908697647.732.png 908697647.733.png 908697647.734.png 908697647.735.png 908697647.736.png 908697647.737.png 908697647.738.png 908697647.739.png 908697647.740.png 908697647.741.png 908697647.743.png 908697647.744.png 908697647.745.png 908697647.746.png 908697647.747.png 908697647.748.png 908697647.749.png 908697647.750.png 908697647.751.png 908697647.752.png 908697647.754.png 908697647.755.png 908697647.756.png 908697647.757.png 908697647.758.png 908697647.759.png 908697647.760.png 908697647.761.png 908697647.762.png 908697647.763.png 908697647.765.png 908697647.766.png 908697647.767.png 908697647.768.png 908697647.769.png 908697647.770.png 908697647.771.png 908697647.772.png 908697647.773.png 908697647.774.png 908697647.777.png 908697647.778.png 908697647.779.png 908697647.780.png 908697647.781.png 908697647.782.png 908697647.783.png 908697647.784.png 908697647.785.png 908697647.786.png 908697647.788.png 908697647.789.png 908697647.790.png 908697647.791.png 908697647.792.png 908697647.793.png 908697647.794.png 908697647.795.png 908697647.796.png 908697647.797.png 908697647.799.png 908697647.800.png 908697647.801.png 908697647.802.png 908697647.803.png 908697647.804.png 908697647.805.png 908697647.806.png 908697647.807.png 908697647.808.png 908697647.810.png 908697647.811.png 908697647.812.png 908697647.813.png 908697647.814.png 908697647.815.png 908697647.816.png 908697647.817.png 908697647.818.png 908697647.819.png 908697647.821.png 908697647.822.png 908697647.823.png 908697647.824.png 908697647.825.png 908697647.826.png 908697647.827.png 908697647.828.png 908697647.829.png 908697647.830.png 908697647.832.png 908697647.833.png 908697647.834.png 908697647.835.png 908697647.836.png 908697647.837.png 908697647.838.png 908697647.839.png 908697647.840.png 908697647.841.png 908697647.843.png 908697647.844.png 908697647.845.png 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