TDA1311A.PDF

INTEGRATED CIRCUITS

DATA SHEET

TDA1311A

Stereo Continuous Calibration DAC

(CC-DAC)

Preliminary specication

Supersedes data of July 1993

File under Integrated Circuits, IC01

1995 Dec 19

Philips Semiconductors

Preliminary specication

Stereo Continuous Calibration DAC

(CC-DAC)

TDA1311A

FEATURES

GENERAL DESCRIPTION

Voltage output

The TDA1311A; AT is a voltage-driven digital-to-analog

converter and is new generation of DAC devices which

embodies the innovative technique of Continuous

Calibration (CC). The largest bit-currents are repeatedly

generated by one single current reference source. This

duplication is based upon an internal charge storage

principle which has an accuracy insensitive to ageing,

temperature matching and process variations.

Space saving packages SO8 or DIP8

Low power consumption

Wide dynamic range (16-bit resolution)

Continuous Calibration (CC) concept

Easy application:

– single 4 to 5.5 V rail supply

– output current and bias current are proportional to the

supply voltage

– integrated current-to-voltage converter

m CMOS

process and features an extremely low-power dissipation,

small package size and easy application. Furthermore, the

accuracy of the intrinsic high coarse-current combined

with the implemented symmetrical offset decoding method

preclude zero-crossing distortion and ensures high quality

audio reproduction. Therefore, the CC-DAC is eminently

suitable for use in (portable) digital audio equipment.

Fast settling time permits 2, 4 and 8 ´ oversampling

(serial input) or double-speed operation at

oversampling

Internal bias current ensures maximum dynamic range

Wide operating temperature range (

C to +85

Compatible with most current Japanese input formats:

time multiplexed, two's complement, TTL

No zero-crossing distortion

Cost efficient.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA1311A

DIP8

plastic dual in-line package; 8 leads (300 mil)

SOT97-1

TDA1311AT

SO8

plastic small outline package; 8 leads; body width 3.9 mm

SOT96-?

1995 Dec 19

The TDA1311A; AT is fabricated in a 1.0

Philips Semiconductors

Preliminary specication

Stereo Continuous Calibration DAC

(CC-DAC)

TDA1311A

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V DD

supply voltage

5.5

I DD

supply current

V DD = 5 V at code 0000H

3.4

6.0

V FS

full scale output voltage

V DD = 5 V

1.8

2.0

2.2

(THD+N)/S total harmonic distortion

plus noise

at 0 dB signal level

0.04

0.07

60 dB signal level

60 dB signal level;

A-weighted

S/N

signal-to-noise ratio at

bipolar zero

A-weighted at code 0000H 86

t cs

current settling time to

0.2

LSB

input bit rate at data input

18.4

Mbits/s

f BCK

clock frequency at clock

input

18.4

MHz

TC FS

full scale temperature

coefcient at analog outputs

(I OL ; I OR )

400

ppm

T amb

operating ambient

temperature

- 40

+85

° C

P tot

total power dissipation

V DD = 5 V at code 0000H

1995 Dec 19

Philips Semiconductors

Preliminary specication

Stereo Continuous Calibration DAC

(CC-DAC)

TDA1311A

BLOCK DIAGRAM

handbook, full pagewidth

LEFT INPUT REGISTER

RIGHT INPUT REGISTER

LEFT OUTPUT REGISTER

RIGHT OUTPUT REGISTER

V OL

I/V

LEFT BIT SWITCHES

RIGHT BIT SWITCHES

I/V

V OR

I OL

I OR

32 (5-BIT)

CALIBRATED

CURRENT

SOURCES

32 (5-BIT)

CALIBRATED

CURRENT

SOURCES

11-BIT

PASSIVE

DIVIDER

11-BIT

PASSIVE

DIVIDER

1 CALIBRATED

SPARE SOURCE

1 CALIBRATED

SPARE SOURCE

REFERENCE

SOURCE

BCK

CONTROL

AND TIMING

TDA1311A

TDA1311AT

V DD

DATA

MBG858

GND

100 nF

Fig.1 Block diagram.

PINNING

SYMBOL

DESCRIPTION

BCK

bit clock input

word select input

DATA

data input

GND

ground

V DD

supply voltage

handbook, halfpage

BCK

V OR

V OL

left channel output

n.c.

TDA1311A

TDA1311AT

n.c.

not connected

DATA

V OL

V OR

right channel output

GND

V DD

MBG859

Fig.2 Pin configuration.

1995 Dec 19

Philips Semiconductors

Preliminary specication

Stereo Continuous Calibration DAC

(CC-DAC)

TDA1311A

FUNCTIONAL DESCRIPTION

A symmetrical offset decoding principle is incorporated

that arranges the bit switching in such a way that the

zero-crossing is performed only by switching the LSB

currents.

The TDA1311A; AT (CC-DAC) accepts serial input data

formats of 16-bit word length. Left and right data words are

time multiplexed. The most significant bit (bit 1) must

always be first. The input data format is shown in Figs 4

and 5.

With a HIGH level on the word select input (WS), data is

placed in the left input register and with a LOW level on the

WS input, data is placed in the right input register (see

Fig.1). The data in the input registers are simultaneously

latched in the output registers which control the bit

switches.

The basic operation of the continuous calibration DAC is

illustrated in Fig.3. The figure shows the calibration and

operation cycle. During calibration of the MOS current

source (see Fig.3a) transistor M1 is connected as a diode

by applying a reference current. The voltage V gs on the

intrinsic gate-source capacitance C gs of M1 is then

determined by the transistor characteristics. After

calibration of the drain current to the reference value I REF ,

the switch S1 is opened and S2 is switched to the other

position (see Fig.3b). The gate-to-source voltage V gs of

M1 is not changed because the charge on C gs is

preserved. Therefore, the drain current of M1 will still be

equal to I REF and this exact duplicate of I REF is now

available at the OUT terminal.

The 32 current sources and the spare current source of the

TDA1311A; AT are continuously calibrated (see Fig.1).

The spare current source is included to allow continuous

converter operation. The output of one calibrated source is

connected to an 11-bit binary current divider consisting of

2048 transistors.

An internal offset voltage V OS is added to the full scale

output voltage V FS ; V OS and V FS are proportional to V DD :

V DD1 /V DD2 =V FS1 /V FS2 =V OS1 /V OS2 .

handbook, full pagewidth

out

I ref

C gs

V gs

C gs

V gs

MBG860

(a)

(b)

(a) = calibration.

(b) = operation.

Fig.3 Calibration principle.

1995 Dec 19

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