AT90S2313.PDF

Features

• Utilizes the AVR ® RISC Architecture

• AVR – High-performance and Low-power RISC Architecture

– 118 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General-purpose Working Registers

– Up to 10 MIPS Throughput at 10 MHz

• Data and Nonvolatile Program Memory

– 2K Bytes of In-System Programmable Flash

Endurance 1,000 Write/Erase Cycles

– 128 Bytes of SRAM

– 128 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– Programming Lock for Flash Program and EEPROM Data Security

• Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler

– One 16-bit Timer/Counter with Separate Prescaler,

Compare, Capture Modes and 8-, 9- or 10-bit PWM

– On-chip Analog Comparator

– Programmable Watchdog Timer with On-chip Oscillator

– SPI Serial Interface for In-System Programming

– Full Duplex UART

• • Special Microcontroller Features

– Low-power Idle and Power-down Modes

– External and Internal Interrupt Sources

• • Specifications

– Low-power, High-speed CMOS Process Technology

– Fully Static Operation

• Power Consumption at 4 MHz, 3V, 25°C

– Active: 2.8 mA

– Idle Mode: 0.8 mA

– Power-down Mode: <1 µA

• I/O and Packages

– 15 Programmable I/O Lines

– 20-pin PDIP and SOIC

• Operating Voltages

– 2.7 - 6.0V (AT90S2313-4)

– 4.0 - 6.0V (AT90S2313-10)

• Speed Grades

– 0 - 4 MHz (AT90S2313-4)

– 0 - 10 MHz (AT90S2313-10)

8-bit

Microcontroller

with 2K Bytes

of In-System

Programmable

Flash

AT90S2313

Description

The AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR RISC

architecture. By executing powerful instructions in a single clock cycle, the

Pin Configuration

(continued)

PDIP/SOIC

Rev. 0839F–10/00

AT90S2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consump-

tion versus processing speed.

The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly

connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction

executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times

faster than conventional CISC microcontrollers.

Figure 1. The AT90S2313 Block Diagram

AT90S2313

AT90S2313

The AT90S2313 provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM,

128 bytes SRAM, 15 general-purpose I/O lines, 32 general-purpose working registers, flexible timer/counters with compare

modes, internal and external interrupts, a programmable serial UART, programmable Watchdog Timer with internal oscilla-

tor, an SPI serial port for Flash memory downloading and two software selectable power-saving modes. The Idle Mode

stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The Power-

down Mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next external

interrupt or hardware reset.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The on-chip In-System Program-

mable Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a

conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Programmable

Flash on a monolithic chip, the Atmel AT90S2313 is a powerful microcontroller that provides a highly flexible and cost-

effective solution to many embedded control applications.

The AT90S2313 AVR is supported with a full suite of program and system development tools including: C compilers, macro

assemblers, program debugger/simulators, in-circuit emulators and evaluation kits.

Pin Descriptions

VCC

Supply voltage pin.

GND

Ground pin.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). PB0 and PB1

also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip analog comparator. The

Port B output buffers can sink 20 mA and can drive LED displays directly. When pins PB0 to PB7 are used as inputs and

are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port B pins are tri-stated

when a reset condition becomes active, even if the clock is not active.

Port B also serves the functions of various special features of the AT90S2313 as listed on page 48.

Port D (PD6..PD0)

Port D has seven bi-directional I/O ports with internal pull-up resistors, PD6..PD0. The Port D output buffers can sink

20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The

Port D pins are tri-stated when a reset condition becomes active, even if the clock is not active.

Port D also serves the functions of various special features of the AT90S2313 as listed on page 53.

RESET

Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the clock is not running. Shorter pulses

are not guaranteed to generate a reset.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip

oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an

external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 3.

Figure 2. Oscillator Connections

MAX 1 HC BUFFER

XTAL2

XTAL1

GND

Note: When using the MCU Oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure.

Figure 3. External Clock Drive Configuration

AT90S2313

AT90S2313

Architectural Overview

The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single clock cycle access

time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands

are output from the register file, the operation is executed, and the result is stored back in the register file – in one clock

cycle.

Figure 4. The AT90S2313 AVR RISC Architecture

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling

efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table

look-up function. These added function registers are the 16-bit X-register, Y-register and Z-register.

The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register

operations are also executed in the ALU. Figure 4 shows the AT90S2313 AVR RISC microcontroller architecture.

In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.

This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing

them to be accessed as though they were ordinary memory locations.

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