hp_compaq_2510P-Quanta-OT2-schematic.pdf

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5
4
3
2
1
Sapp oro 1.0 BLOCK DIAGRA M
14.318MHz
CPU Thermal
Sensor
CPU CORE
P38
Clock Generator
Merom
MAX6657
P04
D
D
CK505
+1.05V/+1.5V
/+1.25V/+1.25VM
P17
P37
478Pins
(Micro-FCBGA)
3VPCU/5VPCU
P35
P4,P5
Ambient Light Sensor
667/800 MHz FSB
1.8V/SMDDR_VTERM/SMDR_VREF
P36
Cable Docking
BATT CHARGER
MAX8724/1908
LVDS
LCD Panel
1 TO 4 USB HUB
P34
P18
Crestline
Singal Channel DDR2
DDR2-SODIMM1
LINE IN
P16
DISCHARGE
R.G,B
1299 uFCBGA
LINE OUT
RJ45
CRT port
P33
P27
CRT PORT
SVIDEO OUT
P7,P8,P9,P10,P11
+3VM_LAN_SW/3V_S5/+3V_CK505/3VSUS/+3V
P39
POWER JACK
C
C
DMI
+5V/5VSUS
P35
PCI-E
SATA/PATA
WLAN MiniCard
P19
HDD (1.8 inch)
P28
ICH8M
PCI-E
PATA
DVD-ROM
P28
USB 2.0
PCI BUS
PCMCIA Controller
LAN
Intel Nineveh-MM
USB PORT 0
P30
P12,P13,P14,P15
Ricoh 5C847
P20,P21
P24,P25
USB PORT 1(POWER
USB)
P30
SMBUS
PCMCIA /SMART CARD
1394
P20
P21
RJ45
B
B
Bluetooth Module
P25
P30
Accelerometer
Azalia
LIS3LV02DL
FingerPrint(AES2501B)
P30
AMP
Audio
AUDIO
JACK
3.3V LPC, 33MHz
SPI
CODEC
TPA6211A
WWAN MiniCard
P23
P23
AD1981
P19
P22,P23
SIM CARD
AMP
USB for Docking
MIC
JACK
P19
P32
SYSTEM
BIOS
TPM (1.2)
TLV2462CDGKR
P23
P23
SLB9635
P31
SMSC KBC1070
MODEM
MDC 1.5
RJ11
A
A
P26
JACK
P30
P30
PROJECT : OT2
FAN
Track
Point
Keyboard
Quanta Computer Inc.
P29
P29
P29
Size
Document Number
Rev
Custom
System Block Diagram
1A
Date:
Thursday, March 22, 2007
Sheet
1
of
42
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INDEX
Power & Ground
Control
Signal
Pg#
Description
NOTE
Label
ACTIVE
Description
VIN
S0, S3, S4, S5.M0.M1.Moff
AC ADAPTER (19V)
1
Schematic Block Diagram
MBAT
S0, S3, S4, S5.M0.M1.Moff
MAIN BATTERY + (10~17V)
2
System Information
D
D
(3_3V)
VCCRTC
S0, S3, S4, S5.M0.M1.Moff
S0, S3, S4, S5.M0.M1.Moff
RTC & KBC POWER
3
System Power Block Diagram
+15V
+15V
4-5
Merom CPU/THERMAL SENSOR
CPU_CORE
S0
CPU CORE POWER (1.25/1.15V)
VRON
7-11
Crestline_
+1.05V
S0
FSB POWER (1.05V)
MAIND
12-15
ICH8_M
+1.05VM
M0.M1
IAMT_ON
DDR II SO-DIMM
16
+3V
S0
MAIND
17
CLOCK GEN
3VSUS
S0, S3
SUSON
18
LCD CONNECTOR / LCD PWR
3V_S5
S0, S3, S4, S5
S5_ON
19
WAN/WWAN /SIM CARD connector
3VPCU
S0, S3, S4, S5.M0.M1.Moff
ALWAYS POWER (3V)
20-21
CARDBUS CONTROLLER
+5V
S0
MAIND
22-23
AUDIO CODEC / AUDIO JACK
C
C
5VSUS
S0, S3
SUSON
24-25
LAN/TRANSFORMER
5V_S5
S0, S3, S4, S5
S5_ON
26
KBC
5VPCU
S0, S3, S4, S5.M0.M1.Moff
ALWAYS POWER (5V)
27
CRT PORT
+1.5V
S0
MAIND
28
HDD / CD-ROM
+1.5VM
M0.M1
IAMT_ON
29
FAN,KB,LEDs,TRACK POINT
1.8VSUS
S0, S3
DDR CORE POWER
SUSON
30
USB,BLUE TOOTH,FINGER PRINT, MDC,TPM
+2.5V
S0
MAINON
POWER SEQUENCE,BIOS
31
SMDDR_VTERM
S0
DDR COMMAND & CONTROL PULL UP POWER
MAINON
32
CABLE DOCKING
SMDDR_VREF
S0, S3
DDR REF POWER
SUSON
33
DISCHARGE
VDDA
S0
AUDIO ANALOG POWER (5V)
MAINON
34
-CHARGER(MAX1908/8724)
B
B
+3V_CK505
M0.M1
IAMT_ON
35
MAX1999(3VPCU/5VPCU)
MAX1992(1.8VSUS/DDR_VTERM)
+3V_LAN_SW
M0.M1
IAMT_ON
36
37
MAX1540 (+1.05V/+1.5V)
+1.25V
S0
MAIND
38
--MAX8736
+1.25VM
M0.M1
IAMT_ON
39
+3VM/+3V_S5/1.25V_M
40
POWER SEQUENCE
PCI DEVICES IRQ ROUTING
PCB STACK UP
SM BUS
DEVICE
IDSEL #
REQ/GNT #
PCI_INT
LAYER 1 : TOP
DEVICE
ADDRESS
BUS
LAYER 2 : GND
CLOCK GENERATOR
LAYER 3 : IN1
A
A
DDR II
LAYER 4 : IN2
LAYER 5 : VCC
Accelemter sensor
LAYER 6 : IN3
PROJECT : OT2
LAYER 7 : GND
LAYER 8 : BOT
CHARGER
Quanta Computer Inc.
Size
Document Number
Rev
CPU THERMAL SENSOR
Custom
System Information
1A
Date:
Thursday, March 22, 2007
Sheet
2
of
42
5
4
3
2
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5
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S5_ON
SYSTEM POWER BLOCK DIAGRAM
S.W
3V_S5
MOS-FET
IAMT_ON
S.W
+3V_CK505
D
D
S.W
MOS-FET
MOS-FET
Adaptor
IAMT_ON
S.W
3VPCU
+3VM_LAN_SW
ALWAYS
MOS-FET
VIN
MAX1999
IAMT_ON
SC4215
+1.25VM
VIN
MAIND
+3V
S.W
MOS-FET
C
C
3VSUS
CHARGER
MAX8724/1908
SUSD
MAIND
+5V
+15V
S.W
MOS-FET
5VSUS
SUSD
5VPCU
ALWAYS
SUSON
S.W
MAINON
BATTERY
MOS-FET
SMDDR_VTERM
B
B
MAX1992
1.8VSUS
TPS51100
SMDDR_VREF
MAINON
MAINON
SC4215
+1.25V
1.5V
VIN
MAX1540
MAIND
S.W
MOS-FET
1.05V_M
+1.05V
IAMAT_ON
VIN
MAINON
VRON
KBC_PW_ON
S5_ON
S5_OND
TC7SH08FU
DISCHARGE
A
A
SLP_S5#
SUSON
SUSD
TC7SH08FU
DISCHARGE
CPU_VID[0..5]
SLP_S3#
MAIND
MAX1907
TC7SH08FU
DISCHARGE
HWPG
CPU_CORE
DPRSLPVR
PROJECT : OT2
STP_CPU#
Quanta Computer Inc.
Size
Document Number
Rev
Custom
1A
System pwr block diagram
Date:
Thursday, March 22, 2007
Sheet
3
of
42
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1
2
3
4
5
6
7
8
H_ADS#(6)
H_A#[3..16]
U21A
H_D#[0..63]
U21B
H_D#[0..63]
(6)
H_A#[3..16]
(6)
H_D#[0..63]
H_D#[0..63](6)
H_A#3
J4
H1
H_D#0
E22
F24
Y22
AB24
V24
V26
V23
T22
U25
U23
H_D#32
A[3]#
ADS#
PAD
T2 5
D[0]#
D[1]#
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
H_A#4
H_D#1
H_D#33
L5
L4
K5
M3
N2
J1
E2
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
BNR#
H_BNR#(6)
H_A#5
H_D#2
H_D#34
G5
E26
H_BPRI#(6)
BPRI#
D[2]#
H_A#6
H_D#3
G22
H_D#35
H_D#37
D[3]#
H_A#7
H_D#4
H_D#36
H5
F21
F23
DEFER#
DRDY#
H_DEFER#(6)
D[4]#
H_A#8
H_D#5
G25
H_DRDY#(6)
D[5]#
H_A#9
H_D#6
H_D#38
E1
E25
DBSY#
H_DBSY#(6)
D[6]#
H_A#10
H_A#12
H_D#7
H_D#39
N3
P5
P2
L2
P4
P1
R1
E23
K24
G24
H_BR0#(6)
A
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
D[7]#
D[8]#
D[9]#
A
H_A#11
F1
H_D#8
H_D#10
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
H_D#40
BR0#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
R11256
1
H_D#9
H_D#41
H_A#13
H_IERR#
H_D#42
D20
2
J24
J23
H22
F26
K22
H23
+1.05V
IERR#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
H_A#14
H_A#16
H_D#11
H_D#43
H_D#44
B3
INIT#
H_INIT#(12)
H_A#15
H_D#12
H4
H_D#13
H_D#45
LOCK#
H_LOCK#(6)
H_D#14
H_D#46
M1
(6)
H_ADSTB#0
ADSTB[0]#
H_REQ#[0..4]
H_D#15
H_D#47
C1
F3
F4
G3
(6)
H_REQ#[0..4]
H_RESET#(6)
RESET#
RS[0]#
RS[1]#
RS[2]#
H_REQ#0
K3
H2
K2
J3
L1
J26
Y26
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
H_RS#0(6)
(6)
H_DSTBN#0
DSTBN[0]#
DSTBN[2]#
H_DSTBN#2(6)
H_DINV#2(6)
H_REQ#1
H26
AA26
H_RS#1(6)
H_RS#2(6)
(6)
H_DSTBP#0
H_DSTBP#2(6)
DSTBP[0]#
DSTBP[2]#
H_REQ#2
H25
U22
(6)
H_DINV#0
DINV[0]#
DINV[2]#
H_REQ#3
G2
TRDY#
H_TRDY#(6)
H_REQ#4
H_D#[0..63]
H_D#[0..63]
(6)
H_D#[0..63]
H_D#[0..63](6)
H_A#[17..35]
G6
E4
H_D#16
N22
K25
P26
R23
AE24
AD24
H_D#48
(6)
H_A#[17..35]
HIT#
HITM#
H_HIT#(6)
D[16]#
D[17]#
D[18]#
D[19]#
D[48]#
D[49]#
H_A#17
H_D#17
H_D#49
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
H_HITM#(6)
H_A#18
H_D#18
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
H_D#50
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
H_A#19
XDP_BPM#0
H_D#19
H_D#51
H_D#52
AD4
AD3
AD1
AC4
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
H_A#20
XDP_BPM#1
Layout Note:
Place voltage
divider within
0.5" of GTLREF
pin
H_D#20
H_D#21
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
H_A#21
XDP_BPM#2
XDP_BPM#4
H_D#53
H_A#22
XDP_BPM#3
H_D#22
H_D#54
H_A#23
AC2
AC1
H_D#23
H_D#55
PRDY#
PREQ#
H_A#24
XDP_BPM#5
H_D#24
H_D#56
H_A#25
H_A#26
XDP_TCK
H_D#25
H_D#57
H_D#59
AC5
AA6
AB3
TCK
TDI
TDO
XDP_TDI
H_D#26
H_D#58
H_A#27
XDP_TDO
H_D#27
H_A#28
AB5
XDP_TMS
+1.05V
H_D#28
AC22
AD23
AF22
AC23
H_D#60
TMS
D[60]#
D[61]#
D[62]#
D[63]#
H_A#29
XDP_TRST#
H_D#29
H_D#61
AB6
TRST#
H_A#30
XDP_DBRESET#
H_D#30
H_D#62
U2
V4
C20
T25
N25
XDP_DBRESET#(14,31)
A[30]#
A[31]#
DBR#
D[30]#
D[31]#
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_D#31
H_D#63
R10575
1
R62
1K/F
B
W3
AA4
AB2
AA3
L26
AE25
B
A[32]#
A[33]#
A[34]#
A[35]#
(6)
H_DSTBN#1
DSTBN[1]#
DSTBN[3]#
H_DSTBN#3(6)
THERMAL
2
M26
AF24
+1.05V
(6)
H_DSTBP#1
H_DSTBP#3(6)
DSTBP[1]#
DSTBP[3]#
N24
AC20
(6)
H_DINV#1
DINV[1]#
DINV[3]#
H_DINV#3(6)
H_PROCHOT#
D21
H_PROCHOT#(39)
PROCHOT#
V1
A24
B25
H_THERMDA
H_THERMDC
V_CPU_GTLREF
CPU_TEST1
A D26
R26
U26
AA1
Y1
COMP0
T11
ADSTB[1]#
THERMDA
THERMDC
GTLREF
COMP[0]
COMP[1]
COMP[2]
COMP[3]
MISC
COMP1
C23
(6)
H_ADSTB#1
TEST1
CPU_TEST2
COMP2
A6
D25
AF26
A26
(12)
H_A20M#
A20M#
TEST2
TEST4
TEST6
A5
C7
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6
C24
COMP3
(12)
H_FERR#
FERR#
THERMTRIP#
PM_THRMTRIP#(7,12)
TEST3
R54
2K/F
C4
(12)
H_IGNNE#
IGNNE#
AF1
E5
B5
D24
H_DPRSTP#(7,12)
H_DPWR#(6)
H_PWRGOOD(12)
H_CPUSLP#(6)
TEST5
DPRSTP#
DPSLP#
DPWR#
H CLK
D5
(12)
H_STPCLK#
STPCLK#
H_DPSLP#(12)
C6
B4
(12)
H_INTR
LINT0
LINT1
A22
A21
CPU_BSEL0
CPU_BSEL1
B22
B23
C21
D6
D7
(12)
H_NMI
BCLK[0]
BCLK[1]
CLK_CPU_BCLK(17)
CLK_CPU_BCLK#(17)
(17)
CPU_BSEL0
BSEL[0]
BSEL[1]
BSEL[2]
PWRGOOD
SLP#
A3
(12)
H_SMI#
SMI#
(17)
CPU_BSEL1
CPU_BSEL2
AE6
(17)
CPU_BSEL2
PSI#
(39)
PSI#
M4
N5
T2
V3
B2
C3
D2
D22
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
Merom Ball-out Rev 1a
DB1A:change for intel
schematic
R124
CPU_TEST3
CPU_TEST5
PAD
T92
CPU_TEST1
CPU_TEST2
1
2
PAD
T6
R119
*1K/F
For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
D3
1
2
RSVD[09]
C49
*1K/F
F6
RSVD[10]
2
1
CPU_TEST4
CPU_TEST6
R125
*0.1U/10V
1
2
Merom Ball-out Rev 1a
*0
C
C
Place C close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.
COMP0
COMP1
COMP2
COMP3
R78
54.9/F
R67
27.4/F
R83
54.9/F
R87
27.4/F
JITP1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TDO
TRSTn
TDI
TMS
GND17
XDP_BPM#5
layout note for H_THERMDA/H_THERMDC - Trace width/Spacing
should be 10/10 mils
XDP_BPM#4
XDP_BPM#3
R76
0
Comp0,2 connect with Zo=27.4ohm,Comp1,3
connect with Zo=55ohm, make those traces
length shorter than 0.5".Trace should be
at least 25 mils away from any other
toggling signal.
R69
*0
XDP_OBS0
XDP_OBS1
+3V
XDP_BPM#2
R71
0
R63
*56/F
+1.05V
XDP_BPM#1
XDP_BPM#0
R66
0
XDP_OBS2
R56
0
XDP_OBS3
R350
100R
H/W MONITOR
XDP_DBRESET#(14,31)
C420
0.1U
U28
SMBCK(17,19,27)
SI stage:no install to avoid leakage current
6657VCC
SMBCK
1
2
3
4
8
VCC
DXP
DXN
-OVT
SMCLK
+1.05V
H_THERMDA
SMBDT
D
7
D
SMDATA
SM BDT(17,19,27)
THERM_ALERT#(14)
H_PWRGOOD
R57
1K/F
H_PWRGD_XDP
CLK_CPU_XDP(17)
R42
54.9/F
C422
2200P
THERM_ALERT#
6
+1.05V
CLK_CPU_XDP#(17)
-ALT
H_THERMDC
R47
1K/F
H_RESET#
5
T5
GND
XDP_DBRESET#
R46
*1K/F
T2
+3V
(35)
SYS_SHDN#
MAX6657/GMT-781
PROJECT : OT2
L_CLKCTLB
XDP_TDO
R41
*54 . 9/F
(7)
L_CLKCTLB
+1.05V
L_CLKCTLA
XDP_TRST#
R40
680
(7)
L_CLKCTLA
Quanta Computer Inc.
XDP_TDI
R36
150
R38
27/F
XDP_TCK
XDP_TMS
R39
39
C50
0.1U
C39
0.1U
Size
Document Number
Rev
DB1A stage:change for change list
Custom
(HOST BUS)/THERMAL
1A
*CONN60_ITP-XDP
DB1A stage:change for change list
Date:
Thursday, March 22, 2007
Sheet
4
of
42
1
2
3
4
5
6
7
8
 
1
2
3
4
5
6
7
8
VCC_CORE
VCC_CORE
U21C
U21D
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
A C10
AB10
AB12
AB14
AB15
A B17
AB18
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
A4
P6
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VSS[001]
VSS[082]
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VCC_CORE
All use 22U 6.3V(+-20%,X5R,0805)Pb-Free.
C44
22U/6.3V
C173
22U/6.3V
C172
22U/6.3V
C171
22U/6.3V
C169
22U/6.3V
A
A
VCC_CORE
C86
22U/6.3V
C85
22U/6.3V
C168
22U/6.3V
C167
22U/6.3V
C174
22U/6.3V
8 inside cavity, north side, secondary layer.
Y6
VSS[106]
VCC_CORE
C81
22U/6.3V
C80
22U/6.3V
C84
22U/6.3V
C83
22U/6.3V
C82
22U/6.3V
+1.05V
G21
V6
VCCP[01]
VCCP[02]
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
+ C106
330U/4V
VCC_CORE
B
B
C143
22U/6.3V
C142
22U/6.3V
C79
22U/6.3V
C145
22U/6.3V
C144
22U/6.3V
DB1A stage:change
to 330u
+1.5V
8 inside cavity, south side, secondary layer.
B26
VCCA[01]
VCC_CORE
C26
VCCA[02]
C156
0.01U/25V
C163
10U/4V
AD6
AF5
AE5
AF4
AE3
AF3
AE2
H_VID0(39)
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
H_VID1(39)
H_VID2(39)
C45
22U/6.3V
C170
22U/6.3V
C138
22U/6.3V
C139
22U/6.3V
C140
22U/6.3V
C141
22U/6.3V
H_VID3(39)
H_VID4(39)
H_VID6(39)
H_VID5(39)
6 inside cavity, north side, primary layer.
Layout Note:
Place C156 near
PIN B26.
AF7
VCCSENSE
VCCSENSE
VCCSENSE(39)
VCC_CORE
AE8
VSS[147]
VSSSENSE
AE7
AE11
VSSSENSE
VSSSENSE(39)
VSS[148]
AE14
AE16
C
VSS[149]
VSS[150]
C
Merom Ball-out Rev 1a
.
AE19
VSS[151]
C48
22U/6.3V
C47
22U/6.3V
C46
22U/6.3V
C43
22U/6.3V
C42
22U/6.3V
C41
22U/6.3V
VCC_CORE
AE23
VSS[152]
AE26
VSS[153]
A2
VSS[154]
AF6
VSS[155]
R45
100/F
AF8
VSS[156]
6 inside cavity, south side, primary layer.
AF11
VSS[157]
AF13
VSS[158]
AF16
VSS[159]
AF19
VSS[160]
VCCSENSE
VSSSENSE
AF21
VSS[161]
A25
VSS[162]
AF25
VSS[163]
+1.05V
R44
100/F
Merom Ball-out Rev 1a
.
C98
0.1U/10V
C87
0.1U/10V
C105
0.1U/10V
C117
0.1U/10V
C96
0.1U/10V
C123
0.1U/10V
Route VCCSENSE and VSSSENSE
traces at 27.4ohms and
length matched to within 25
mil. Place PU and PD within
2 inch of CPU.
Layout out:
Place these
inside
socket
cavity on
North side
secondary.
D
D
PROJECT : OT2
Quanta Computer Inc.
Size
Document Number
Rev
Custom
Merom(POWER/NC)
1A
Date:
Thursday, March 22, 2007
Sheet
5
of
42
1
2
3
4
5
6
7
8
 

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