EMIF02-USB01F2.pdf

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2 LINES EMI FILTER INCLUDING ESD PROTECTION
®
EMIF02-USB01F2
IPAD™
2 LINES EMI FILTER
INCLUDING ESD PROTECTION
PRODUCT CHARACTERISTICS
ESD protection and EMI filtering for:
■ USB port
DESCRIPTION
The EMIF02-USB01F2 is a highly integrated array
designed to suppress EMI / RFI noise for USB
port filtering.
The EMIF02-USB01F2 flip-chip packaging means
the package size is equal to the die size.
Additionally, this filter includes an ESD protection
circuitry which prevents the protected device from
destruction when subjected to ESD surges up to
15 kV.
BENEFITS
Flip-Chip
(8 Bumps)
Table 1: Order Code
Part Number
Marking
EMIF02-USB01F2
FF
■
2 lines low-pass-filter + 2 lines ESD protection
Figure 1: Pin Configuration (Ball side)
High efficiency in EMI filtering
■
■
Lead free package
32 1
Very low PCB space consuming: < 2.5 mm 2
■
■
Very thin package: 0.65 mm
Pup
Vbus
A
High efficiency in ESD suppression
(IEC61000-4-2 level 4)
■
DZ
B
High reliability offered by monolithic integration
■
■
High reducing of parasitic elements through
integration & wafer level packaging.
D+
in
D+
out
C
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2
Level 4
GND
D
15kV (air discharge)
8kV (contact discharge)
D-
in
D-
out
E
Figure 2: Configuration
Pup
Vbus
1.3K
33
DZ
D+ out
D+ in
GND
33
D- out
D- in
TM: IPAD is a trademark of STMicroelectronics.
October 2004
REV. 1
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EMIF02-USB01F2
Table 2: Absolute Ratings (T amb = 25°C)
Symbol
Parameter and test conditions
Value
Unit
T j
Junction temperature
125
°C
T op
Operating temperature range
- 40 to + 85
°C
T stg
Storage temperature range
- 55 to + 150
°C
Table 3: Electrical Characteristics (T amb = 25°C)
Symbol Parameter
V BR Breakdown voltage
I RM Leakage current @ V RM
V RM Stand-off voltage
V CL
Clamping voltage
Rd
Dynamic impedance
I PP
Peak pulse current
R I/O Series resistance between Input &
Output
C line Input capacitance per line
slope: 1/Rd
Symbol
Test conditions
Min.
Typ.
Max.
Unit
V BR
I R = 1 mA
6
V
I RM
V RM = 3V
0.5
µ
A
C line
@ 0V
40
45
pF
R 1, R 2
Tolerance ± 5%
33
Ω
R 3
Tolerance ± 5%
1.30
k
Ω
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EMIF02-USB01F2
Figure 3: S21 (dB) attenuation measurement
Figure 4: Analog crosstalk measurements
EMIF02-USB01: filtering response of lines C1/C3 and E1/E3
0.00
0.00
dB
dB
-5.00
-10.00
-10.00
-20.00
-15.00
-30.00
-20.00
-40.00
-25.00
-50.00
-30.00
-60.00
-35.00
-70.00
-40.00
-80.00
-90.00
-45.00
-100.0
-50.00
1.0M
3.0M
10.0M
30.0M
100.0M
300.0M
1.0G
3.0G
1.0M
3.0M
10.0M
30.0M
100.0M 300.0M
1.0G
3.0G
f/Hz
E1_E3
Frequency/Hz
C1_C3
Figure 5: ESD response to IEC61000-4-2 (+15kV
air discharge) on one input V(in) and on one
output (Vout)
Figure 6: ESD response to IEC61000-4-2 (-15kV
air discharge) on one input V(in) and on one
output (Vout)
Vin : 10V/d
Vin : 5V/d
Vout : 10V/d
Vout : 5V/d
100ns/d
100ns/d
Figure 7: Capacitance versus reverse applied
voltage (typical)
40
35
30
25
20
15
VR(V)
10
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
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0.00
438464309.001.png 438464309.002.png
EMIF02-USB01F2
Figure 8: Aplac model (resistors, diodes and bumps and ground connections)
3.8nH
R_1k3
A1, A3, B2, C1, C3, E1, E3
Cbump Rsubump
D2
C1
A3
I/O
bulk
Csub
Csub
0.15nH
rsub_1k3
rsub_1k3
Lbump
D02_usb
100m
D2
bulk
Rbump
bulk
0.15nH
R_33R
0.23nH
C3
D02_usb
D02_Nw
Lhole
cap_33R
Csub
Csub
cap_33R
caphole
rsub_33R
rsub_33R
Lgnd_D
Rsub_D
Rhole
D2
bulk
bulk
0 . 3nH
R_33R
0.7nH
E1
E3
cap_33R
Csub
Csub
cap_33R
rsub_33R
rsub_33R
bulk
Figure 9: Aplac model parameters
R_33R 33.9
cap_33R 1.2pF
Model D02_Nw
BV=100
IBV=1m
CJO=6.8p
M=0.3333
RS=2
VJ=0.6
TT=100n
Model D02_usb
BV=16
IBV=1m
CJO=Cz
M=0.3333
RS=2
VJ=0.6
TT=100n
R_1k3 1.3k
Cz29pF
Rsub_D 100
Csub0.3pF
Rsub_33R 15
Rsub_1k3 50
lhole10pH
Rhole400m
Caphole0.4pF
Lgnd_D 150pH
Lbump50pH
Rbump50m
Cbump1.5pF
Rsubump150
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Csub
Csub
R_33R 33.9
cap_33R 1.2pF
R_1k3 1.3k
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EMIF02-USB01F2
Figure 10: Ordering Information Scheme
EMIF yy - xxx zz Fx
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip-Chip
x = 1: 500µm, Bump = 315µm
= 2: Leadfree Pitch = 500µm, Bump = 315µm
= 3: Leadfree Pitch = 400µm, Bump = 250µm
Figure 11: FLIP-CHIP Package Mechanical Data
700 ± 50
315 ± 50
650µm ± 65
1.27mm ± 50µm
Figure 12: Foot print recommendations
Figure 13: Marking
365
240
Copper pad Diameter :
250µm recommended , 300µm max
Dot, ST logo
xx = marking
z = packaging location
yww = datecode
(y = year
ww = week)
E
Solder stencil opening : 330µm
Solder mask opening recommendation :
340µm min for 315µm copper pad diameter
xxz
y ww
220
All dimensions in µm
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