doc0856.pdf

(1185 KB) Pobierz
AVR Instruction Set Manual
Instruction Set Nomenclature
Status Register (SREG)
SREG: Status Register
C:
Carry Flag
Z:
Zero Flag
N:
Negative Flag
8-bit
Instruction Set
V:
Two’s complement overflow indicator
S:
N ⊕ V, For signed tests
H:
Half Carry Flag
T:
Transfer bit used by BLD and BST instructions
I:
Global Interrupt Enable/Disable Flag
Registers and Operands
Rd:
Destination (and source) register in the Register File
Rr:
Source register in the Register File
R:
Result after instruction is executed
K:
Constant data
k:
Constant address
b:
Bit in the Register File or I/O Register (3-bit)
s:
Bit in the Status Register (3-bit)
X,Y,Z:
Indirect Address Register
(X=R27:R26, Y=R29:R28 and Z=R31:R30)
A:
I/O location address
q:
Displacement for direct addressing (6-bit)
Rev. 0856H–AVR–07/09
378041534.049.png 378041534.050.png 378041534.051.png 378041534.052.png 378041534.001.png 378041534.002.png 378041534.003.png
 
I/O Registers
RAMPX, RAMPY, RAMPZ
Registers concatenated with the X-, Y-, and Z-registers enabling indirect addressing of the whole data space on MCUs with
more than 64K bytes data space, and constant data fetch on MCUs with more than 64K bytes program space.
RAMPD
Register concatenated with the Z-register enabling direct addressing of the whole data space on MCUs with more than 64K
bytes data space.
EIND
Register concatenated with the Z-register enabling indirect jump and call to the whole program space on MCUs with more
than 64K words (128K bytes) program space.
Stack
STACK: Stack for return address and pushed registers
SP:
Stack Pointer to STACK
Flags
⇔ :
Flag affected by instruction
0 :
Flag cleared by instruction
1 :
Flag set by instruction
- :
Flag not affected by instruction
2
AVR Instruction Set
0856H–AVR–07/09
378041534.004.png 378041534.005.png 378041534.006.png
AVR Instruction Set
The Program and Data Addressing Modes
The AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to the Program
memory (Flash) and Data memory (SRAM, Register file, I/O Memory, and Extended I/O Memory). This section describes
the various addressing modes supported by the AVR architecture. In the following figures, OP means the operation code
part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. To generalize, the
abstract terms RAMEND and FLASHEND have been used to represent the highest location in data and program space,
respectively.
Note: Not all addressing modes are present in all devices. Refer to the device spesific instruction summary.
Register Direct, Single Register Rd
Figure 1. Direct Single Register Addressing
The operand is contained in register d (Rd).
Register Direct, Two Registers Rd and Rr
Figure 2. Direct Register Addressing, Two Registers
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).
3
0856H–AVR–07/09
378041534.007.png 378041534.008.png 378041534.009.png 378041534.010.png 378041534.011.png 378041534.012.png 378041534.013.png 378041534.014.png 378041534.015.png 378041534.016.png 378041534.017.png 378041534.018.png 378041534.019.png 378041534.020.png 378041534.021.png 378041534.022.png 378041534.023.png
I/O Direct
Figure 3. I/O Direct Addressing
Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.
Note: Some complex AVR Microcontrollers have more peripheral units than can be supported within the 64 locations reserved in the
opcode for I/O direct addressing. The extended I/O memory from address 64 to 255 can only be reached by data addressing,
not I/O addressing.
Data Direct
Figure 4. Direct Data Addressing
Data Space
31
20 19
16
0x0000
OP
Rr/Rd
Data Address
15
0
RAMEND
A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source
register.
4
AVR Instruction Set
0856H–AVR–07/09
378041534.024.png 378041534.025.png 378041534.026.png 378041534.027.png 378041534.028.png 378041534.029.png 378041534.030.png 378041534.031.png 378041534.032.png 378041534.033.png 378041534.034.png 378041534.035.png 378041534.036.png 378041534.037.png 378041534.038.png
AVR Instruction Set
Data Indirect with Displacement
Figure 5. Data Indirect with Displacement
Data Space
0x0000
15
0
Y OR Z - REGISTER
15
10
6
5
0
OP
Rr/Rd
q
RAMEND
Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instruction
word. Rd/Rr specify the destination or source register.
Data Indirect
Figure 6. Data Indirect Addressing
Data Space
0x0000
15
0
X, Y OR Z - REGISTER
RAMEND
Operand address is the contents of the X-, Y-, or the Z-register. In AVR devices without SRAM, Data Indirect Addressing is
called Register Indirect Addressing. Register Indirect Addressing is a subset of Data Indirect Addressing since the data
space form 0 to 31 is the Register File.
5
0856H–AVR–07/09
378041534.039.png 378041534.040.png 378041534.041.png 378041534.042.png 378041534.043.png 378041534.044.png 378041534.045.png 378041534.046.png 378041534.047.png 378041534.048.png

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin