VHDL-Handbook.pdf

VHDL

handbook

Contents

LexicaL eLements ............................................................. 4

Deinition ................................................................................................4

Character set ...........................................................................................4

Separators ...............................................................................................4

Delimiters ...............................................................................................4

Identiiers ................................................................................................4

LiteraLs .................................................................................. 5

Numerical literals....................................................................................5

Enumeration literals................................................................................5

String literals...........................................................................................5

Bit string literals .....................................................................................5

The NULL literal ....................................................................................5

reserved words................................................................. 6

syntax ...................................................................................... 7

Standards.................................................................................................7

The Backus-Naur-format ........................................................................7

types and objects ............................................................. 8

Predeined types......................................................................................8

Predeined subtypes ................................................................................8

Types and subtypes .................................................................................9

ARRAY.................................................................................................10

RECORD ..............................................................................................11

ACCESS TYPES (pointers) .................................................................12

Aggregates ............................................................................................13

GROUP .................................................................................................14

ATTRIBUTE.........................................................................................15

Constant declaration .............................................................................16

Variable declaration ..............................................................................17

Signal declaration .................................................................................18

File declaration/File handling ...............................................................19

File reading (TEXTIO) .........................................................................20

File writing (TEXTIO) .........................................................................21

ALIAS...................................................................................................22

Libraries............................................................................... 23

LIBRARY and USE..............................................................................23

design units ........................................................................ 24

PACKAGE DECLARATION...............................................................24

PACKAGE BODY................................................................................25

ENTITY ................................................................................................26

ARCHITECTURE................................................................................27

CONFIGURATION..............................................................................28

sequentiaL statements............................................... 29

WAIT ....................................................................................................29

IF...........................................................................................................30

CASE ....................................................................................................31

LOOP, NEXT and EXIT .......................................................................32

FUNCTION ..........................................................................................33

PROCEDURE.......................................................................................34

Version 3.1

Contents

RETURN ..............................................................................................35

Variable assignment ..............................................................................36

Signal assignment .................................................................................37

concurrent and sequentiaL statements........ 38

ASSERT/REPORT................................................................................38

Subprogram call....................................................................................39

concurrent statements ............................................ 40

PROCESS .............................................................................................40

WHEN ..................................................................................................41

SELECT................................................................................................42

BLOCK.................................................................................................43

generic parameters and generate..................... 44

GENERIC/GENERIC MAP .................................................................44

GENERATE..........................................................................................45

components........................................................................ 46

Component declaration.........................................................................46

Component instantiation.......................................................................47

Default coniguration ............................................................................48

Coniguration speciication...................................................................49

Coniguration declaration .....................................................................50

predefined attributes ................................................ 51

Attributes on types................................................................................51

Attributes on arrays...............................................................................52

Attributes on signals .............................................................................53

Attributes on named entities .................................................................54

ieee ........................................................................................... 56

VHDL standards ...................................................................................56

Predeined packages..............................................................................56

STANDARD ....................................................................................................56

TEXTIO ...........................................................................................................57

STD_LOGIC_1164 ..........................................................................................58

NUMERIC_BIT ...............................................................................................60

NUMERIC_STD..............................................................................................61

MATH_REAL ..................................................................................................63

MATH_COMPLEX .........................................................................................64

vHdL guide ........................................................................... 66

Introduction...........................................................................................66

File notation ..........................................................................................66

Predeined packages..............................................................................66

VHDL syntax ........................................................................................66

Simulation and synthesis ......................................................................69

vHdL’87 and vHdL’93, differences ........................... 70

index........................................................................................ 74

Lexical elements

Deinition

• The text of a design ile is a sequence of lexical elements.

• Lexical elements are divided into the following groups:

- delimiter

- identiier (may be a reserved word)

- abstract literal (integer or loating point type)

- character literal (a graphical character surrounded by ‘, e.g.: ‘H’)

- string literal (a sequence of graphical characters surrounded by ”, e.g.: ”HAR-

DI”)

- bit string literal (a sequence of extended digits * surrounded by ”, e.g.: ”011”)

- comment (preceded by -- and is valid until the end of the line)

LRM

§ 13

Character set

The character set in VHDL’87 is 128 characters, in VHDL’93 it is 256

characters (see page 8, 56). The character set is divided into seven groups

– Uppercase letters , Digits , Special characters , The space characters , Lo-

wercase letters , Other special characters and format effector .

Separators

Separators are used to separate lexical elements. An example is the space

character (SPACE).

Delimiters

A delimiter is one of the following characters or character combinations:

& ‘ ( ) * + , - . / : ; < = > | [ ]

=> ** := /= >= <= <>

Identiiers

An identiier is either a name or a reserved word (see page 6). There are

two kinds of identiiers:

• Basic identiiers

- Must begin with a letter.

- May contain letters and digits.

- May contain the character ‘_’, but not as irst or last character and not more than

one in a row.

- Are not case-sensitive.

• Extended identiiers **

- May contain letters and digits.

- Begins and ends with the character ‘\’.

- The \ character may be included in the identiier, but must then be doubled, e.g.:

\ab\\cd\

- May include an unlimited amount of all graphical characters and in any order.

- Are case-sensitive.

* Possible values for an extended digit is determined by the base for the bit

string literal (see page 5).

** New to VHDL’93

Literals

A literal is a written value of a type. The are in total ive different kinds

of literals.

LRM

§ 7.3.1, 13.4-7

Numerical literals

[ universal_integer , universal_real , literals of physical types ]

Numerical literals of universal_integer do not include a point, literals of

universal_real do include a point, while literals of physical types may

include a point and must include a unit.

All numerical literals may include:

• ‘_’ to increase readability, e.g.: 1_000

• ‘E’ or ‘e’ to include an exponent, e.g.: 5E3 (i.e. 5000).

• ‘#’ to describe a base, e.g.: 2#1010# (i.e. 10). It is possible to have a base

between 2 and 16.

A physical type must include a space between its value and its unit, e.g.:

1 ns

Enumeration literals

[e.g.: BIT, BOOLEAN, CHARACTER]

Enumeration literals are graphical characters or identiiers (see page 4), e.g.:

(reset, start, ‘a’, ‘A’).

String literals

[e.g.: STRING)

String literals are one-dimensional arrays including character literals. They

always begin end end with a ” (the ” character may be included in the literal,

but must then be doubled, e.g.: ”A ”” character”).

Bit string literals

[e.g: BIT_VECTOR, STD_LOGIC_VECTOR * ]

Bit string literals are one-dimensional arrays including extended digits (see

page 4). They always begin and end with a ”.

It is possible to include a base for a bit string literal. There are three bases:

B - Binary (possible values: 0 - 1).

O - Octal (possible values: 0 - 7). Each value is replaced by three

values (‘0’ or ‘1’).

X - Hexadecimal (possible values: 0 - 9, A - F, a - f). Each value is

replaced by four values (‘0’ or ‘1’).

A bit string literal may include ‘_’ to increase readability, e.g.: ”0100_

0111”.

The NULL literal

[NULL]

The NULL literal is only used for access types, i.e. pointers (see page 12),

and imply that the pointer is empty, i.e. not pointing anywhere.

* New to VHDL’93 (see page 73)

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika: