lf411.pdf

February 1995

LF411 Low Offset, Low Drift

JFET Input Operational Amplifier

General Description

These devices are low cost, high speed, JFET input opera-

tional amplifiers with very low input offset voltage and guar-

anteed input offset voltage drift. They require low supply

current yet maintain a large gain bandwidth product and fast

slew rate. In addition, well matched high voltage JFET input

devices provide very low input bias and offset currents. The

LF411 is pin compatible with the standard LM741 allowing

designers to immediately upgrade the overall performance

of existing designs.

These amplifiers may be used in applications such as high

speed integrators, fast D/A converters, sample and hold

circuits and many other circuits requiring low input offset

voltage and drift, low input bias current, high input imped-

ance, high slew rate and wide bandwidth.

Features

Y Internally trimmed offset voltage

0.5 mV(max)

Y Input offset voltage drift

10 m V/ § C(max)

Y Low input bias current

50 pA

Y Low input noise current

0.01 pA/

Y Wide gain bandwidth

3 MHz(min)

Y High slew rate

10V/ m s(min)

Y Low supply current

1.8 mA

Y High input impedance

10 12 X

Y Low total harmonic distortion A V e 10,

k 0.02%

R L e 10k, V O e 20 Vp-p, BW e 20 Hz b 20 kHz

Y Low 1/f noise corner

50 Hz

Y Fast settling time to 0.01%

2 m s

Typical Connection

Ordering Information

LF411XYZ

X indicates electrical grade

Y indicates temperature range

``M'' for military

``C'' for commercial

Z indicates package type

``H'' or ``N''

Connection Diagrams

Metal Can Package

TL/H/5655±5

TL/H/5655±1

Top View

Note: Pin 4 connected to case.

Order Number LF411ACH

or LF411MH/883*

See NS Package Number H08A

Simplified Schematic

Dual-In-Line Package

TL/H/5655±7

TL/H/5655±6

Top View

Order Number LF411ACN,

LF411CN or LF411MJ/883*

See NS Package Number

N08E or J08A

BI-FET II TM is a trademark of National Semiconductor Corporation.

*Available per JM38510/11904

C 1995 National Semiconductor Corporation

TL/H/5655

RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

(Note 8)

H Package

N Package

Power Dissipation

(Notes 2 and 9)

670 mW

T j max

150 § C

115 § C

LF411A

LF411

i j A

162 § C/W (Still Air)

120 § C/W

Supply Voltage

g 22V

g 18V

65 § C/W (400 LF/min

Air Flow)

Differential Input Voltage g 38V

g 30V

Input Voltage Range

(Note 1)

i j C

20 § C/W

g 19V

g 15V

Operating Temp.

Range

Output Short Circuit

Duration

(Note 3)

Continuous Continuous

Storage Temp.

Range

b 65 § C s T A s 150 § C b 65 § C s T A s 150 § C

Lead Temp.

(Soldering, 10 sec.)

260 § C

ESD Tolerance

Rating to be determined.

DC Electrical Characteristics (Note 4)

Symbol

Parameter

Conditions

LF411A

LF411

Units

Min Typ Max Min Typ Max

V OS

Input Offset Voltage R S e 10 k X ,T A e 25 § C

0.3 0.5

0.8

2.0 mV

D V OS / D T Average TC of Input R S e 10 k X (Note 5)

7 10

m V/ § C

Offset Voltage

(Note 5)

I OS

Input Offset Current V S e g 15V

T j e 25 § C

25 100

100

(Notes 4, 6)

T j e 70 § C

T j e 125 § C

I B

Input Bias Current V S e g 15V

T j e 25 § C

50 200

200

(Notes 4, 6)

T j e 70 § C

T j e 125 § C

R IN

Input Resistance

T j e 25 § C

10 12

A VOL

Large Signal Voltage V S e g 15V, V O e g 10V,

50 200

25 200

V/mV

Gain

R L e 2k, T A e 25 § C

Over Temperature

25 200

15 200

V/mV

V O

Output Voltage Swing V S e g 15V, R L e 10k

g 12 g 13.5 g 12 g 13.5

V CM

Input Common-Mode

g 16 a 19.5

g 11 a 14.5

Voltage Range

b 16.5

b 11.5

CMRR Common-Mode

R S s 10k

80 100

70 100

Rejection Ratio

PSRR Supply Voltage

(Note 7)

80 100

70 100

Rejection Ratio

I S

Supply Current

1.8 2.8

1.8

3.4 mA

AC Electrical Characteristics (Note 4)

Symbol

Parameter

Conditions

LF411A

LF411

Units

Min Typ Max Min Typ Max

Slew Rate

V S e g 15V, T A e 25 § C 10 15

8 15

V/ m s

GBW Gain-Bandwidth Product

V S e g 15V, T A e 25 § C 3

2.7 4

MHz

e n

Equivalent Input Noise Voltage T A e 25 § C, R S e 100 X ,

nV/ S 0

f e 1 kHz

i n

Equivalent Input Noise Current T A e 25 § C, f e 1 kHz

0.01

pA/ S 0 Hz

Note 1: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.

Note 2: For operating at elevated temperature, these devices must be derated based on a thermal resistance of i j A.

Note 3: These devices are available in both the commercial temperature range 0 § C s TA s 70 § C and the military temperature range b 55 § C s TA s 125 § C. The

temperature range is designated by the position just before the package type in the device number. A ``C'' indicates the commercial temperature range and an ``M''

indicates the military temperature range. The military temperature range is available in ``H'' package only.

Note 4: Unless otherwise specified, the specifications apply over the full temperature range and for V S eg 20V for the LF411A and for V S eg 15V for the LF411.

V OS ,I B , and I OS are measured at V CM e 0.

Note 5: The LF411A is 100% tested to this specification. The LF411 is sample tested to insure at least 90% of the units meet this specification.

Note 6: The input bias currents are junction leakage currents which approximately double for every 10 § C increase in the junction temperature, T j . Due to limited

production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient

temperature as a result of internal power dissipation, P D .T j e T A ai jA P D where i jA is the thermal resistance from junction to ambient. Use of a heat sink is

recommended if input bias current is to be kept to a minimum.

Note 7: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice, from

g 15V to g 5V for the LF411 and from g 20V to g 5V for the LF411A.

Note 8: RETS 411X for LF411MH and LF411MJ military specifications.

Note 9: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate

outside guaranteed limits.

Typical Performance Characteristics

Input Bias Current

Supply Current

Positive Common-Mode

Input Voltage Limit

Negative Common-Mode

Input Voltage Limit

Positive Current Limit

Negative Current Limit

Output Voltage Swing

TL/H/5655±2

Typical Performance Characteristics (Continued)

Gain Bandwidth

Bode Plot

Slew Rate

Distortion vs Frequency

Undistorted Output

Voltage Swing

Open Loop Frequency

Response

Common-Mode Rejection

Ratio

Power Supply

Rejection Ratio

Equivalent Input Noise

Voltage

Open Loop Voltage Gain

Output Impedance

Inverter Settling Time

TL/H/5655±3

Pulse Response R L e 2k X ,C L 10 pF

Small Signal Inverting

Small Signal Non-Inverting

Large Signal Inverting

Large Signal Non-Inverting

Current Limit (R L e 100 X )

TL/H/5655±4

Application Hints

The LF411 series of internally trimmed JFET input op amps

(BI-FET II TM ) provide very low input offset voltage and guar-

anteed input offset voltage drift. These JFETs have large

reverse breakdown voltages from gate to source and drain

eliminating the need for clamps across the inputs. There-

fore, large differential input voltages can easily be accom-

modated without a large increase in input current. The maxi-

mum differential input voltage is independent of the supply

voltages. However, neither of the input voltages should be

allowed to exceed the negative supply as this will cause

large currents to flow which can result in a destroyed unit.

Exceeding the negative common-mode limit on either input

will force the output to a high state, potentially causing a

reversal of phase to the output. Exceeding the negative

common-mode limit on both inputs will force the amplifier

output to a high state. In neither case does a latch occur

since raising the input back within the common-mode range

again puts the input stage and thus the amplifier in a normal

operating mode.

Exceeding the positive common-mode limit on a single input

will not change the phase of the output; however, if both

inputs exceed the limit, the output of the amplifier may be

forced to a high state.

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