54ACT163.pdf

November 1998

54AC163 • 54ACT163

Synchronous Presettable Binary Counter

General Description

The ’AC/’ACT163 are high-speed synchronous modulo-16

binary counters. They are synchronously presettable for ap-

plication in programmable dividers and have two types of

Count Enable inputs plus a Terminal Count output for versa-

tility in forming synchronous multistage counters. The ’AC/

’ACT163 has a Synchronous Reset input that overrides

counting and parallel loading and allows the outputs to be si-

multaneously reset on the rising edge of the clock.

n Synchronous counting and loading

n High-speed synchronous expansion

n Typical count rate of 125 MHz

n Outputs source/sink 24 mA

n ’ACT163 has TTL-compatible inputs

n Standard Microcircuit Drawing (SMD)

— ’AC163: 5962-89582

— ’ACT163: 5962-91723

Features

n I CC reduced by 50%

Logic Symbols

Names

Description

CEP

Count Enable Parallel Input

CET

Count Enable Trickle Input

Clock Pulse Input

Synchronous Reset Input

P 0 – P 3

Parallel Data Inputs

Parallel Enable Input

Q 0 –Q 3

Flip-Flop Outputs

Terminal Count Output

DS100275-1

IEEE/IEC

DS100275-2

FACT ™ is a trademark of Fairchild Semiconductor Corporation.

DS100275

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Connection Diagrams

Pin Assignment

for DIP and Flatpak

Pin Assignment

for LCC

DS100275-3

DS100275-4

Functional Description

The ’AC/’ACT163 counts in modulo-16 binary sequence.

From state 15 (HHHH) it increments to state 0 (LLLL). The

clock inputs of all flip-flops are driven in parallel through a

clock buffer. Thus all changes of the Q outputs occur as a re-

sult of, and synchronous with, the LOW-to-HIGH transition of

the CP input signal. The circuits have four fundamental

modes of operation, in order of precedence: synchronous re-

set, parallel load, count-up a nd hold. Four co ntr ol

inputs — Synchronous Reset (SR), Parallel Enable (PE),

Count Enable Parallel (CEP) and Count Enable Trickle

(CET) — determine the mode of oper atio n, as shown in the

Mode Select Table. A LOW signal on SR overrides counting

and parallel loading and allows all output s to go LOW on the

next rising edge of CP. A LOW signal on PE overrides count-

ing and allows information on the Parallel Data (P n ) inputs to

be lo ade d int o t he flip-flops on the next rising edge of CP.

With PE and SR HIGH, CEP and CET permit counting when

both are HIGH. Conversely, a LOW signal on either CEP or

CET inhibits counting.

The ’AC/’ACT 163 use s D-type edge-triggered flip-flops and

changing the SR, PE, CEP and CET inputs when the CP is

in either state does not cause errors, provided that the rec-

ommended setup and hold times, with respect to the rising

edge of CP, are observed.

The Terminal Count (TC) output is HIGH when CET is HIGH

and counter is in state 15. To implement synchronous multi-

stage counters, the TC outputs can be used with the CEP

and CET inputs in two different ways.

Figure 1 shows the connections for simple ripple c arry , in

which the clock period must be longer th an th e CP to TC de-

lay of the first stage, plus the cumul ative CET to TC delays of

the intermediate stages, plus the CET to CP setup time of

the last stage. This total delay plus setup time sets the upper

limit on clock frequency. For faster clock rates, the carry loo-

kahead connections shown in Figure2are recommended. In

this scheme the ripple delay through the intermediate stages

commences with the same clock that causes the first stage

to tick over from max to min in the Up mode, or min to max

in the Down mode, to start its final cycle. Since this final

cycle takes 16 clocks to complete, there is plenty of time for

the ripple to progress through the intermediate stag es. The

critical timing that limits the clock period is the CP to TC de-

lay of the fir st s tage plus the CEP to CP setup time of the last

stage. The TC output is subject to decoding spikes due to in-

ternal race conditions and is therefore not recommended for

use as a clock or asynchronous reset for flip-flops, registers

or counters.

Logic Equations: Count Enable = CEP • CET • PE

TC = Q 0 • Q 1 • Q 2 • Q 3 • CET

Mode Select Table

CET

CEP

Action on the Rising

Clock Edge ( N )

Reset (Clear)

Load (P n

Q n )

Count (Increment)

No Change (Hold)

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

State Diagram

DS100275-5

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State Diagram (Continued)

DS100275-8

FIGURE 1.

DS100275-9

FIGURE 2.

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DS100275-6

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V CC )

Recommended Operating

Conditions

Supply Voltage (V CC )

’AC

2.0V to 6.0V

−0.5V to +7.0V

’ACT

4.5V to 5.5V

DC Input Diode Current (I IK )

V I = −0.5V

Input Voltage (V I )

0VtoV CC

−20 mA

Output Voltage (V O )

0VtoV CC

V I = V CC + 0.5V

+20 mA

Operating Temperature (T A )

54AC/ACT

DC Input Voltage (V I )

−0.5V to V CC + 0.5V

−55˚C to +125˚C

DC Output Diode Current (I OK )

V O = −0.5V

Minimum Input Edge Rate (

−20 mA

’AC Devices

V IN from 30% to 70% of V CC

V CC @ 3.3V, 4.5V, 5.5V

V O = V CC + 0.5V

+20 mA

DC Output Voltage (V O )

−0.5V to V CC + 0.5V

125 mV/ns

DC Output Source

or Sink Current (I O )

Minimum Input Edge Rate (

± 50 mA

’ACT Devices

V IN from 0.8V to 2.0V

V CC @ 4.5V, 5.5V 125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, without

exception, to ensure that the system design is reliable over its power supply,

temperature, and output/input loading variables. National does not recom-

mend operation of FACT ™ circuits outside databook specifications.

DC Characteristics for ’AC Family Devices

54AC

DC V CC or Ground Current

per Output Pin (I CC or I GND )

± 50 mA

Storage Temperature (T STG )

−65˚C to +150˚C

Junction Temperature (T J )

CDIP

175˚C

T A =

Symbol

Parameter

V CC

Units

Conditions

(V)

−55˚C to +125˚C

Guaranteed

Limits

V OUT = 0.1V

V IH

Minimum High Level

3.0

2.1

Input Voltage

4.5

3.15

or V CC − 0.1V

5.5

3.85

V OUT = 0.1V

V IL

Maximum Low Level

3.0

0.9

Input Voltage

4.5

1.35

or V CC − 0.1V

5.5

1.65

I OUT = −50 µA

V OH

Minimum High Level

3.0

2.9

Output Voltage

4.5

4.4

5.5

5.4

(Note 2)

V IN = V IL or V IH

3.0

2.4

I OH = −12 mA

4.5

3.7

I OH = −24 mA

5.5

4.7

I OH = −24 mA

I OUT = 50 µA

V OL

Maximum Low Level

3.0

0.1

Output Voltage

4.5

0.1

5.5

0.1

(Note 2)

V IN = V IL or V IH

3.0

0.50

I OL =12mA

4.5

0.50

I OL =24mA

5.5

0.50

I OL =24mA

± 1.0

V I = V CC , GND

I IN

Maximum Input

5.5

µA

Leakage Current

V OLD = 1.65V Max

I OLD

Minimum Dynamic

Output Current (Note 3)

5.5

V OHD = 3.85V Min

I OHD

5.5

−50

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