CC_1988_i0002.pdf

MICROCOMPUTER APPLICATIONS

TABLE of CONTENTS

PUBLISHER

Stephen J. Walters

EDITORIAL:

The Core Audience by stem Ciarcia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

EDITORIAL DIRECTOR

Steve Ciarcia

FEATURES:

EXECUTIVE EDITOR

Harv Weiner

Circuit Cellar Neighborhood Strategic Defense Initiative

The Ballistic Dynamics oj Plastic Soda Bottles

by stwecii& FdNii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

I-ECHNICAL EDITORS

Kenneth Davidson

Je jj Bachiochi

The Home Satellite Weather Center--Part 2:

NTSC Encoder Alignment and System Overview

by r&ilk voorhe6.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CONTRIBUTING EDITORS

Thomas Cantrell

Edward Nisley

Personal-Computer-Based Instrumentation

Build a I-Channel Temperature Logging and Data Reduction System

byTOmRiley

CIRCULATION DIRECTOR

Jeannette Dojan

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CIRCULATION ASSISTANT

Diane Morey

DEPARTMENTS:

Reader’s Ink

Letters to the Editor

PRODUCTION MANAGER

Tricia Dziedzinski

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BUSINESS MANAGER

Daniel Rodrigues

Visible Ink

Letters to the Circuit Cellar INK Research Sta jj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

STAFF RESEARCHERS

Northeast

Eric Albert

William Curlew

Richard Sawyer

Robert Stek

Midwest

John Elson

Tim McDonough

West Coast

Frank Kuechmann

Mark Voorhees

the Techie by phil ~cmmor~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

ConnecTime

Excerpts from the Circuit Cellar BBS by Ken Davidron . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Firmware Furnace

Digitizing In jrared Signals by Ed Nirley . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Circuit Cellar BBS - 24 EC.. 300/1200/2400 bps, 8 Bits, No parity, 1 Stop Bit, 205-871-1981

Cover Illuetration by Robert Tinney

The schematics provided in Circuit Cellar INK are drawn using SCHEMA from Omation

Inc. Ml programa and schematic8 in Circuit Cellar INK have been carefully reviewed to ennun

that their performance ia in accordance with the specifications deecribed and program8 art

CIRCUIT CELLAR. INK (ISSN 0896-

8986) in publbhed bi-monthly by Circuit

Cellar Incorporated, 4 Park Street, Suite 20,

ported on the Circuit Cellar BBS for electronic tranrfer by rubscribers.

Circuit Cellar INK maken no warrantier and 811sumes no reaponribility or liability of any kinc

Vernon, CT06066 (203-876-2751). Second-

claaa poetage applied for at Vernon, CT. One

year (6 inuer) charter subscription rate

U.S.A. and porsersionr $14.96, Canada

$17.95, all other countries $26.95. All rub-

scriptionordempayableinUSfundronly,via

for errors in these programs or schematics or for the consequences of any such errors

Furthermore, because of the poeaible variation in the quality and condition of materials ant

workmanship of reader-aesembled projects, Circuit Cellar INK disclaims any renponribility fo

the rafe &d proper function of reader-assembled projects baaed upon or from planm

descriptions, or information published in Circuit Cellar INK.

international postal money order or check

drawn on US bank. Direct subscription or-

dem to Circuit Cellar INK, Subscriptions,

P.O.BoxS378, Wallingford,CTO6494orcall

(205)875-2199.

duction of this publication in whole or in part without written consent from Circuit Cella

Incorporated is prohibited.

POSTMASTER: Please send address changes to Circuit Cellar INK, Circulation Dept., P.C

Box 3378, Wallingford, CT. 06494

Ink Spot -- Guest Editorial

Leonardo

March/Atxil 1988

7 The Core Audience

lhe essential ingredient in any successful publication is a dedicated core audience. The core audience consists

of readers who personally identify with the purpose and value of a publication. In the extreme, publications with

strong identities even develop unique “personalities” that core readers form lasting relationships with.

Depending upon a publication’s purpose, the composition and necessity for a dedicated core audience varies.

I don’t generally think of Good Housekeeping or TV Guide as being particularly concerned about core audiences,

for example. But, a technical magazine like Scientific American, which is designed for a minimum level of

scientific understanding and interest, has almost a cult following.

Publishers have to be careful when they change their goals. Unlike time-critical news or event-based

magazines, core-audience-critical technical publications have to be constantly aware of their prime directives

so that they don’t dilute or ignore the core audience in a frenzy to meet financial objectives.

A circulation manager once described the delicate process of increasing publication revenues to me in the

following way: Think of carefully breaking an egg in the center of a spinning turntable. At the center is a well-

defined and boundaried area (the yoke) surrounded by an almost infinitely expandable unboundaried area (the

white). Metaphorically speaking, the yoke is the core readership and the white is the general-interest audience

of the publication.

Expansion and contraction of readership and revenue is dynamic. The rotation rate of the turntable represents

a complex compromise of editorial, reader, and revenue objectives. When the platter spins at a reasonable rate,

following a well-planned path, the yoke will remain intact and the white will expand out uniformly. If, as the

result of an abrupt change in objectives, however, the platter is spun very fast or with sudden acceleration, the

situation changes radically.

Initial appearances can actually misrepresent actual results. The white will indeed expand out very quickly

and appear to demonstrate substantial gain but, left unchecked, this applied energy can rupture the yoke causing

the core audience to spill out at the same rate of expansion.

Reader profiles are not just emotionless demographics. Specialized journals like INK have a vested interest

in a cohesive and dedicated core audience. The uniqueness of a technical journal is that its readers are also its

authors. While we are often disparagingly called “techies,” INK truly has a nonsuperficial core reader and

experience shows most of these readers are also experts at the center of innovation. As a core reader of INK

you are in good company!

Successful technical journals are those that have forged a proper balance between business and editorial

objectives. I for one am dedicated to keeping INK’s direction consistent with its significance. I am proud to be

a techie, and I make no bones about it!

Circuit Cellar ink

Dear Steve,

Cantrell’s article on “RISC vs Reality, an Exercise in

Acronyms.” It appears as if the one-sided, so called

“facts” about RISC CPUs and the performance they can

provide is something that Mr. Cantrell doesn’t seem to

fully understand. RISC CPUs may not be for every

user, but if it is speed and performance you desire in

your computing needs you just may have found what

you’ve been looking for.

RISC doesn’t mean cutting corners on the hardware,

but I will agree that the software will need to be much

smarter on these types of systems. For some of us

advanced “hackers,” computational performance is all

that matters. Software or no. I hope he reads your

opening editorial. It is what’s inside the box that counts!

Not to mention, your specific needs and/or applications

when it comes to the RISC. Steve, if I may be so bold,

let me direct my additional comments to Mr. Cantrell

personally.

Frankly, I’m shocked Mr. Cantrell. RISC -- is for

student computers? Acronyms! What are people going

to think about RISC when they read your article? The

power that can be achieved from a RISC CPU offers

tremendous and dramatic performance improvements

over traditional computer architectures. By reducing

the use of microcode, limiting references to main

memory, and using RISC optimizing compilers that

manage and analyze the instruction flow, the results are

quite clear. Compilers maximize the concurrency of

such operations as storage, branching, and floating-

point instructions. The machine code they produce

improves application performance by maximizing

grouping similar operations.

Notice the “key” word here is “application”! This

optimization of instruction flow reduces wait states and

increases the efficiency and performance of the RISC

CPU. Using simpler instruction sets and minimizing

microcode translations result in CPU instructions being

executed in one machine cycle and increased through-

put respectively. In addition, if instructions are uni-

form in length, the need to order or schedule instruc-

tions prior to their execution is reduced. The result is

a smoother flow of instructions through the CPU and

faster execution times. Such architectures most often

depend less on memory referencing for instruction

fetching and translation as well; that further increases

As a nonelectrical engineer, I have followed your

articles in BYTE for many years. I’ve put together a few

of your kits. I have always admired your ability to write

about electronics in an understandable way. Occasion-

ally I have plagerized portions of your work or made

a few copies for the students in my classes.

I’ve been interested in instrumentation throughout

my professional career (as an agricultural engineer) and

have always played with electronics. Several years ago

I struck out on my own (nonengineering) but found that

I missed it so I returned to another university.

While there, I homed in on the BCC52 and taught a

course in experimental data acquisition using it. The

more I used it the more I liked it. I am now developing

a course in Sensors and Control for students headed into

industrial jobs, and food engineering.

I have always wished there was more of what you

write about. I have subscribed to Popular Electronics

since high school and now Radio Electronics and

Computer Smyth. I welcome Circuit Cellar INK and

just thought you should hear from one of the silent

(electronic) majority.

Keep up the tutorials; I always learn something new.

Kenneth A. Jordan

Tucson, AZ

Dear Ken,

Thanks for the vote of confidence, Ken. I will endeavor

to keep Circuit Cellar INK both entertaining and infor-

mative. I looked over the class materials and BASIC-

52 programs you sent. The way it is presented could

benefit many people. Perhaps you should upload these

class materials to the Circuit Cellar BBS and share them

with other readers.

-- Steve

Dear Steve,

It has been a long time coming, but you’ve finally

got it in published form...BRAVO! I can’t wait for the

next issue. I would like to comment on Mr. Tom

March/Am-i1 1988

system efficiency.

Speaking of memory, RISC CPUs employ data and

instruction caches that greatly reduce the need for

argument and instruction fetching thereby accelerating

system speed. Instruction set complexity is a VERY

BIG DEAL! System performance may only be one

factor in achieving success in the market, but depend-

ing on what market you’re in, it may be everything you

need.

Don’t get me wrong, I enjoyed your editorial and

look forward to a response from you or Steve concern-

ing my somewhat biased view of the RISC CPU. In

closing, I thought you might be interested in my

favorite toy, which is what I’ve been referring to

throughout this letter.

It is the Prime PCXL 5521 Graphics Workstation. A

supermini VME computer utilizing a fully customized

CMOS VLSI, IO-MIPS, 32-bit RISC CPU; 4-MFLOPS

coprocessor; 12 MB ECC MOS memory; 17 VLSI lo-

MHz highly pipelined graphics engines handling

145,000 3D 32-bit FLOP coordinates per second,

accelerated by 14 custom-VLSI processors for graph-

ics management, providing 16.7 million RGB, 24-bit

displayable colors, 1280 x 1024-pixel resolution for

true, real-time interaction with 3D graphics and com-

plex 4D transformations.

Enough acronyms for you? My business would be

next to impossible without the RISC CPU. I’m now an

independent designer of ultra high resolution computer

animated graphics for the post video production

industry, and previously have been a systems telecom-

munications engineer for several years, working spe-

cifically with the D.O.D. For writing, I use a PC/XT

compatible, manufactured by Ericsson Information

Systems and Microsoft. Word processing by MultiMate

Advantage 3.6.

it as “Instruction set complexity has little to do with

system performance.”

I agree with most of what you say, because most of

it isn’t about instruction sets. Rather, as is often the case,

what starts as a pitch for RISC evolves into a discussion

of cache, multiregister sets, and optimizing compilers.

These were all deemed worthy long ago. Thirty lashes

with an Ethernet cable (and not the thin stuff)!

“RISC CPUs employ data and instruction caches that

greatly reduce the need for argument and instruction

fetching, accelerating system speed.” Arrgghh -- more

RISCSpeak! Do you mean to imply that CISCs don’t,

or can’t, have cache ? What does data cache have to do

with instruction set complexity?

As for “Such architectures most often depend less on

memory referencing for instruction fetching...,” even

RISC proponents admit the architecture exhibits more,

not less, instruction traffic than CISC. For example,

comparing two memory locations requires three instruc-

tions on a RISC (LD,LD,CMP) versus one instruction on

a CISC (CMP). The real argument is how much the

increase in number of instructions executed is offset by

faster instruction execution.

Even your workstation RISC CPU needs a floating-

point coprocessor (or a more optimal optimizer). You

have complex instructions after all!

The key factors for system performance are multi-

processing (architecture) and process/speed (implem-

entation). These, not instruction set complexity, are

what separate a CRAY from a PC.

I appreciate your comments as a fellow INK reader.

“What’s inside the box still counts,” not what they say.

Tom Cantrell

Dear Steve,

Rich Gaskill, President - The Graphics Workshop

Garland, TX

Congratulations on your new publication, and I

wish you great success. It is badly needed because most

of the other magazines contain nothing but low-level

applications and advertising hype.

I don’t hesitate to tell our readers about other good

publications (a little different than BYTE’s attitude!!),

and I’ll announce it [INK] in the next issue.

Dear Mr. Gaskill,

I’m sorry if you were disturbed by my editorial. I

went out of my way to say a few good things about RISC.

I’m all for anything that helps keep the big guys honest.

I concede that as a marketing issue, RISC has a big

impact (it is giving a lot of people an excuse to change).

Witness all the excitement over the AT&T-Sun affair.

My original statement, “Instruction set complexity is

not that big a deal,” is open to interpretation. I’ll restate

Best of Luck,

Art Carlson

Editor/Publisher

The Computer Journal

Columbia Falls, MT 1111

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