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Texas Instruments Incorporated
Power Management
Understanding output voltage limitations of
DC/DC buck converters
By John Tucker
Low Power DC/DC Applications
Introduction
Product datasheets for DC/DC converters typically show
an operating range for input and output voltages. These
operating ranges may be broad and in some cases may
overlap. It is usually not possible to derive any arbitrary
output voltage from the entire range of permissible input
voltages. There are several factors that can cause this,
including the internal reference voltage, the minimum
controllable ON time, and the maximum duty-cycle
constraints.
Ideal buck-converter operation
Consider the theoretical, ideal buck converter shown in
Figure 1. The buck converter is used to generate a lower
output voltage from a higher DC input voltage.
If the losses in the switch and catch diode are ignored,
then the duty cycle, or the ratio of ON time to the total
period, of the converter can be expressed as
V
V
OUT
IN
D
=
.
(1)
The duty cycle is determined by the output of the error
amplifier and the PWM ramp voltage as shown in Figure 2.
The ON time starts on the falling edge of the PWM ramp
voltage and stops when the ramp voltage equals the out-
put voltage of the error amplifier. The output of the error
amplifier in turn is set so that the feedback portion of the
output voltage is equal to the internal reference voltage.
This closed-loop feedback system causes the output volt-
age to regulate at the desired level. If the output of the
Figure 1. Theoretical, ideal buck converter
V IN
Ramp
Generator
S1
Feedback
Voltage
L OUT
V OUT
–
Control Logic
and
Gate Drive
–
+
R1
+
PWM
Comparator
S2
Error
Amplifier
C OUT
+
V REF
R2
Figure 2. Typical PWM waveforms at
duty-cycle extremes and midpoint
PWM Ramp
Error Amplifier
Output
Duty Cycle
0%
100%
50%
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Analog Applications Journal
2Q 2008
High-Performance Analog Products
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Power Management
Texas Instruments Incorporated
error amplifier falls below the PWM ramp minimum, then
a 0% duty cycle is commanded, the converter will not
switch, and the output voltage is 0 V. If the error-amplifier
output is above the PWM ramp peak, then the command-
ed duty cycle is 100% and the output voltage is equal to
the input voltage. For error-amplifier outputs between
these two extremes, the output voltage will regulate to
maximum achievable output voltage. Most important of
these are the on resistance of the high- and low-side
switch elements, and the series resistance of the output
inductor. Taking these losses into account, we can now
express the duty cycle of the converter as
V
+
I
×
(
r
+
R
)
OUT
OUT
DS
2
L
D
=
) ,
(6)
VI
−
×
(
r
−
r
IN
OUT
DS
1
DS
2
V
=×
DV
.
(2)
OUT
IN
where r DS1 is the on resistance of the high-side switch, S1;
r DS2 is the on resistance of the low-side switch, S2; and R L
is the output-inductor series resistance. Since the loss
terms are added to the numerator and subtracted from
the denominator, the duty cycle increases with increasing
load current relative to the ideal duty cycle. This has the
effect of increasing the available minimum voltage. The
worst-case situation for determining the minimum avail-
able output voltage occurs when the input voltage is at its
maximum specification, the output current is at the mini-
mum load specification, and the switching frequency is at
its maximum value. The minimum output voltage is then
Practical limitations
For the ideal buck converter, any output voltage from 0 V
to V IN may be obtained. In actual DC/DC converter circuits,
there are practical limitations. It has been shown that the
output voltage is proportional to the duty cycle and input
voltage. Given a particular input voltage, there are limita-
tions that prevent the duty cycle from covering the entire
range from 0 to 100%. Most obvious is the internal refer-
ence voltage, V REF . Normally, a resistor divider network as
shown in Figure 1 is used to feed back a portion of the
output voltage to the inverting terminal of the error ampli-
fier. This voltage is compared to V REF ; and, during steady-
state regulation, the error-amplifier output will not go
below the voltage required to maintain the feedback volt-
age equal to V REF . So the output voltage will be
V
=
t
×
f
×
[
V
−
I
OUT
(min)
on
(min)
s
(max)
IN
(max)
OUT
(min)
(7)
×
(
r
−
r
2 ]][
)
−
I
×
(
r
+
R
].
DS
1
DS
OUT
(min)
DS
2
L
In contrast, the loss terms decrease the available maxi-
mum voltage, and the worst-case conditions occur at the
minimum input voltage and maximum load current. Since
the limiting factor, maximum duty cycle, is specified as a
percentage, the switching frequency is not relevant. The
maximum available output voltage is given by
R
R
1
2
⎛
⎜
⎞
⎟
V
=
V
+
1.
(3)
OUT
REF
As R2 approaches infinity, the output voltage goes to
V REF so that the output cannot be regulated to below the
reference voltage.
There may also be constraints on the minimum control-
lable ON time. This may be caused by limitations in the
gate-drive circuitry or by intentional delays. This minimum
controllable ON time puts an additional constraint on the
minimum achievable V OUT :
V
=
D
×
[
V
−
I
×
(
r
−
r
)]
OUT
(max)
max
IN
(min)
OUT
(max)
DS
1
DS
2
(8)
−
[
I
×
(
r
+
R
)] .
OUT
(max)
DS
2
L
Examples
Now we can consider a typical application and calculate
the minimum and maximum output voltages. For this
example, the input-voltage range is 20 to 28 V, and the
load current required is 2 to 3 A. Table 1 shows typical
datasheet characteristics of the DC/DC converter.
First we need to calculate the minimum available output
voltage by substituting the following parameters into
V
=
t
×
V
×
f
,
(4)
where t on(min) is the minimum controllable ON time and f s
is the switching frequency.
The duty cycle may also be constrained at the upper
end. In many converters, a dead time is required to charge
the high-side switching FET gate-drive circuit. Feedforward
circuitry may also cause a flattening of the PWM ramp
waveform as the slope of the PWM ramp is increased while
the period remains constant. This will limit the maximum
output voltage with respect to V IN . Typically, if there is a
maximum duty-cycle limit, it will be expressed as a per-
centage, and the maximum output voltage will be
OUT
(min)
on
(min)
IN
s
Table 1. Typical datasheet characteristics of DC/DC converter
PARAMETER
MINIMUM NOMINAL
MAXIMUM
Reference Voltage (V)
--
1.221
--
Switching Frequency (kHz)
400
500
600
Minimum Controllable ON Time (ns)
--
150
200
V
=×
V
D
max .
(5)
OUT
(max)
IN
Maximum Duty Cycle (%)
87
--
--
Effect of circuit losses
So far we have assumed that the components in the circuit
are ideal and lossless. Of course, this is not the case.
There are conduction losses associated with the compo-
nents that are important in determining the minimum and
FET r DS(on) (V IN < 10 V) (mΩ)
--
150
--
FET r DS(on) (V IN = 10 to 30 V) (m
Ω
)
--
100
200
12
Analog Applications Journal
High-Performance Analog Products
2Q 2008
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Texas Instruments Incorporated
Power Management
Equation 7: t on(min) = 200 ns, f s(max) = 600 kHz, r DS1 = r DS2
= r DS(on) = 100 m Ω , V IN(max) = 28 V, and I OUT(min) = 2 A.
Since the worst-case conditions occur when t on(min) and f s
are at the maximum and the loss terms are at a minimum,
we use the appropriate specifications from Table 1. We also
need to supply the series resistance of the output inductor.
A typical value for the series resistance is 25 m
ages would be 2.838 V and 18.525 V, respectively. The
nonsynchronous buck converter is capable of lower or
higher output voltages than the synchronous buck con-
verter under the same conditions.
Conclusion
While the ideal buck converter can theoretically provide
any output voltage from V IN down to 0 V, practical limita-
tions do exist. The output voltage cannot go below the
internal reference voltage, and internal circuit operation
may limit the minimum ON time and maximum duty cycle.
Additionally, real-world circuits contain losses. These losses
can act to extend the duty cycle at higher load currents
and may be used to one’s advantage when output-voltage
extremes exist.
Related Web sites
Ω
, so
Equation 7 can be solved as
V
OUT(min)
. =××−×− −×+
200
600
[
28
2
( .
0 1
0 1
. )]
[
2
( .
0 1
0 025
.
)]
=
3 306 .
V
To calculate the maximum output voltage, we need to
substitute the following values into Equation 8: r DS1 = r DS2
= r DS(on)(max) = 200 mW, V IN(min) = 20 V, I OUT(max) = 3 A,
D max = 87%, and R L = 25 mW. With these values,
Equation 8 becomes
V OUT(max)
.
=
087
×
[
20
−
3
×
(.
02 02
−
.)] [
−
3
×
(.
02
+
025
. )]
=
16 725 V
.
.
In the example, both switch elements, S1 and S2, are
considered active switches. This configuration is the syn-
chronous buck regulator. If both switches are internal to
the converter’s integrated circuit, they will likely have the
same on-resistance characteristics, and I OUT × (r DS1 – r DS2 )
will be zero. In many applications, the low-side switch
element is replaced with a passive element, usually a
Schottky diode. These devices do not specify an on resis-
tance but instead have a forward conduction voltage; so,
for the nonsynchronous buck converter, the minimum and
maximum output voltages are
V
=
t
×
f
×
[
V
−
(
I
OUT
(min)
on
(min)
s
(max)
IN
(max)
OUT
(min)
(9)
×
r
)
−
V
]
−
(
I
×−
R
V
DS
1
d
OUT
(min)
L
d
and
V
=
D
×
[
V
−
(
I
×
r
)
−
V
]
OUT
(max)
max
IN
(min)
OUT
(max)
DS
1
d
(10)
−
(
I
×
R
)
−
V
.
OUT
(max)
L
If the diode forward-voltage drop is 0.4 V, then for the
example given, the minimum and maximum output volt-
13
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High-Performance Analog Products
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