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Texas Instruments Incorporated
Interface (Data Transmission)
Designing with digital isolators
By Thomas Kugelstadt
Senior Applications Engineer
Introduction
The purpose of this article is to help engineers use the
Texas Instruments (TI) ISO72xx family of digital isolators
to design galvanically isolated systems in the shortest time
possible. The article explains the basic operating principle
of the TI isolator, suggests where to place it within a system
design, and recommends guidelines for an electromagnetic-
compatible (EMC) circuit-board design.
Operating principle
The isolator in Figure 1 is based on a capacitive-isolation-
barrier technique. The device consists of two data channels
—a high-frequency channel with a bandwidth ranging from
100 kbps up to 150 Mbps, and a low-frequency channel
covering the range from 100 kbps down to DC.
In principle, a single-ended input signal entering the
high-frequency channel is split into a differential signal via
the inverter gate at the input. The subsequent capacitor-
resistor networks differentiate the signal into transients,
which are then converted into differential pulses by two
comparators. The comparator outputs drive a NOR-gate
flip-flop whose output feeds an output multiplexer. A
decision logic (DCL) at the driving output of the flip-flop
measures the durations between signal transients. If the
duration between two consecutive transients exceeds a
certain time limit, as in the case of a low-frequency signal,
the DCL forces the output multiplexer to switch from the
high- to the low-frequency channel.
Because low-frequency input signals require the internal
capacitors to assume prohibitively large values, a pulse-
width modulator (PWM) is used to modulate these signals
with the carrier frequency of an internal oscillator (OSC),
thus creating a frequency high enough to pass the capaci-
tive barrier. As the input is modulated, a low-pass filter
(LPF) is needed to remove the high-frequency carrier
from the actual data before it is passed on to the output
multiplexer.
Figure 1. Block diagram of a digital capacitive isolator
Isolation Barrier
OSC
LPF
Low-Frequency
Channel
(
DC to 100 kbps
)
V
REF
PWM
0
OUT
IN
1
S
DCL
High-Frequency
Channel
(
100 kbps to 150 Mbps
)
V
REF
21
Analog Applications Journal
2Q 2009
www.ti.com/aaj
High-Performance Analog Products
Interface (Data Transmission)
Texas Instruments Incorporated
meaning that a high at input C sets output
––
to high, and
a high at
––
sets D to high. Because the comparator output
pulses are of short duration, there will be times when both
outputs are low. During this time the flip-flop stores its
previous output condition. Since the signal at
––
is identical
to the input signal in shape and phase,
––
becomes the out-
put of the high-frequency channel and is connected to the
output multiplexer.
While input signals with symmetrical duty cycles cause
equidistant pulses at the comparator outputs, asymmetri-
cal signals (shown in the “Data Transfer” timing diagram
in Figure 2) move the comparator pulses closer to each
other to maintain the shape and phase relationships of the
input signal.
High-frequency-channel operation
Figure 2 presents the high-frequency channel and the
waveforms at specific points of the signal chain. The
single-ended input signal is split into the differential signal
components, A and
––
. Each signal component is then differ-
entiated into the transients, B and
––
. The subsequent com-
parators compare the differential transients to one another.
As long as the positive input of a comparator has a higher
potential than its negative input, the comparator output
will present a logical high, thus converting an input tran-
sient into a short output pulse.
The output pulses set and reset a NOR-gate flip-flop.
From the “NOR-Gate Truth Table” in Figure 2 we see that
the NOR-gate configuration presents an inverting flip-flop,
Figure 2. Timing in high-frequency-channel operation
NOR-Gate Truth Table
A
B
C
C
C
D
D
D
L
L
H
H
L
H
L
H
S*
H
L
L
S
L
H
L
V
REF
IN
D
C
*S = Store previous condition
A
B
Clock Transfer
(Duty Cycle = 50:50)
Data Transfer
(Duty Cycle = 90:10)
IN =
A
IN =
A
A
A
B
B
B
B
C
C
C
C
D
D
D
D
22
High-Performance Analog Products
www.ti.com/aaj
2Q 2009
Analog Applications Journal
Texas Instruments Incorporated
Interface (Data Transmission)
Low-frequency-channel operation
As shown in Figure 3, a PWM modulates slow input signals
with a high-frequency carrier such that, at location A, a
high-level input yields a 90:10 duty cycle, and a low-level
input yields a 10:90 duty cycle. From there on, signal proc-
essing is identical to the asymmetrical signal processing in
the high-frequency channel. The only exception is that the
high-frequency content of
––
, the low-frequency channel, is
filtered by an R-C LPF before being passed on to the out-
put multiplexer, E.
Isolator technology and requirements
The successful proof of the single isolator’s ability to trans-
mit wideband data (from DC to above 150 Mbps) inspired
TI to fabricate unidirectional and bidirectional devices in
dual-, triple-, and quad-channel versions that accommo-
date the most common digital interfaces encountered in
industrial applications (see Figure 4). All TI digital isolators
utilize single-ended, 3-V/5-V CMOS-logic switching tech-
nology. Their nominal supply-voltage range is specified
Figure 3. Timing in low-frequency-channel operation
IN
CLK
A
B
C
OSC
A
D
E
LPF
B
V
REF
IN
PWM
C
D
C
A
B
D
E
Figure 4. TI family of stand-alone digital isolators
ISO721
ISO722
ISO7220
ISO7221
V
GND2
V
CC
2
V
1
2
3
4
5
6
7
8
V
1
2
3
4
5
6
7
8
V
1
2
3
4
5
6
7
8
V
CC2
OUT
OUT
GND2
V
OUT
IN
GND1
1
2
3
4
5
6
7
8
V
IN
OUT
GND2
CC2
CC1
A
B
CC1
CC1
CC1
A
B
CC2
A
IN
IN
EN
IN
IN
A
B
V
GND1
OUT
GND2
V
GND1
OUT
GND2
CC1
CC1
B
GND1
ISO7230
ISO7231
ISO7240CF
V
CC2
GND2
OUT
OUT
OUT
NC
EN
GND2
V
CC2
GND2
OUT
OUT
IN
NC
EN
GND2
V
CC2
GND2
OUT
OUT
OUT
OUT
EN
GND2
V
CC1
GND1
IN
IN
IN
NC
NC
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC1
GND1
IN
IN
IN
IN
DIS
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC1
GND1
IN
IN
A
B
C
A
B
C
A
B
A
B
A
B
C
D
A
B
C
D
OUT
C
C
NC
EN
1
2
GND
ISO7240
ISO7241
ISO7242
V
V
V
V
CC1
GND1
IN
IN
IN
IN
NC
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC2
CC2
CC2
CC1
CC1
GND2
OUT
OUT
OUT
GND1
IN
IN
IN
OUT
GND2
OUT
OUT
GND1
IN
IN
GND2
OUT
OUT
IN
IN
A
B
C
D
A
B
C
A
B
C
D
A
B
A
B
A
B
OUT
IN
OUT
OUT
C
C
D
C
D
OUT
D
D
EN
GND2
EN
EN
GND2
EN
GND1
EN
1
2
1
2
GND1
GND2
23
Analog Applications Journal
2Q 2009
www.ti.com/aaj
High-Performance Analog Products
Interface (Data Transmission)
Texas Instruments Incorporated
from 3.3 V to 5 V for both supplies, V
CC1
and V
CC2
, and
allows any combination of these values.
It is important for the designer to keep in mind that
digital isolators, due to their single-ended design
structure, do not conform to any specific interface
standard and are intended only for isolating single-
ended, 3-V/5-V digital signal lines.
Figures 5 to 7 give examples of isolated interfaces for
SPI, RS-232, and RS-485 applications. Note that the isola-
tor is always placed between the data controller (i.e., the
microcontroller or UART) and a data converter or line
transceiver, regardless of the interface type or standard.
Figure 5 presents the simplest isolator application. Here
the entire circuit constitutes a single-ended, low-voltage
system in which a digital isolator connects the SPI interface
of a controller with the SPI interface of a data converter.
The most commonly applied TI isolators in SPI interfaces
are ISO7231 and ISO7241, often designated as 3- and
4-channel SPI isolators.
The full-blown, isolated RS-232 interface in Figure 6
requires two quad isolators because six control signals are
required in addition to the actual data lines, RX and TX.
Although the entire system is single-ended, the high-
voltage requirements of the symmetrical, ±13-V bus supply
make it necessary to galvanically isolate the data link
between the UART and the low-voltage side of the bus
transceiver.
Figure 5. Isolated SPI interface
3V
3V
3V
ISO
3V
ISO
Micro-
controller
SS
SCK
MOSI
MISO
SS
SCK
SIMO
SOMI
ADC
Figure 6. Isolated RS-232 interface
+12 V
5V
ISO
5V
ISO
3 V
3V
RX
RX
TX
D0 –D7
D0–D7
TX
DBS-9
Connector
RTS
RTS
MEMR or I/OR
DTR
DTR
IOR
5
MEMW or I/OW
9
IOW
RS-232
Drivers and
Receivers
INTR
UART
INT
3V
5V
ISO
RESET
RESET
DSR
6
DSR
A0
1
A0
CD
CD
A1
A1
CTS
CTS
A2
A2
RI
RI
–12 V
24
High-Performance Analog Products
www.ti.com/aaj
2Q 2009
Analog Applications Journal
Texas Instruments Incorporated
Interface (Data Transmission)
As in the previous example, the isolation of the RS-485
interface in Figure 7a occurs between the controller and
the bus transceiver. Despite the entire interface circuit
being a low-voltage system, the differential nature of the
transmission bus requires prior isolation on the single-
ended side. Due to the simplicity of this interface, it was
possible to integrate the isolator function into the RS-485
transceiver circuit as shown in Figure 7b, thus providing
an application-specific isolator device featuring low cost
and a low component count.
To simplify the selection of an appropriate isolator for a
specific application, Table 1 provides a comprehensive
overview of TI digital isolators. Of the five different speed
grades for isolators—A, B, C, CF, and M—all but the M
version possess internal low-pass noise filters at the data
inputs and are therefore recommended for use in noisy
environments. The high-speed version, M, requires exter-
nal input filtering when used in noisy environments. This
is accomplished by connecting a filter capacitor from an
Figure 7. Isolated RS-485 interface
3V
ISO
3V
ISO
3V
3V
D
DE
DOUT
DIR
DIN
Host
Controller
RE
R
(a) Discrete
3V
ISO
3V
3V
D
DE
RE
R
DOUT
Host
Controller
DIR
DIN
(b) Integrated
Table 1. Overview of TI stand-alone and application-specific isolators
MAX.
DATA RATE*
(Mbps)
MAX.
PROP. DELAY*
(ns)
MAX. CH/CH
OUTPUT SKEW*
(ns)
TYPICAL OUTPUT
RISE TIME*
(ns)
ISOLATOR
TYPE
SPEED
GRADE
INPUT
THRESHOLD
DEVICE
TTL
100
24
—
1
Single
ISO721
/722
M
CMOS
150
16
—
1
A
1
475
15
1
B
TTL
5
70
3
1
Dual
ISO7220/
7221
C
25
42
1
1
M
CMOS
150
16
1
1
A
1
95
2
2
TTL
Triple
ISO7230/
7231
C
25
42
2
2
M
CMOS
150
23
1
2
A
1
95
2
2
TTL
ISO7240/
7241
/7242
C
25
42
2
2
Quad
M
CMOS
150
23
1
2
ISO7240
CF
TTL
25
42
2
2
1.3 (XTR)
125 (RCV)
900 (XTR)
1 (RCV)
ISO3082
TTL
0.2
—
RS-485
Half-Duplex
340 (XTR)
100 (RCV)
185 (XTR)
2 (RCV)
ISO15
TTL
1
—
45 (XTR)
125 (RCV)
7 (XTR)
1 (RCV)
ISO3088
TTL
20
—
1.3 (XTR)
125 (RCV)
900 (XTR)
1 (RCV)
ISO3080
TTL
0.2
—
RS-485
Full-Duplex
340 (XTR)
100 (RCV)
185 (XTR)
2 (RCV)
ISO35
TTL
1
—
45 (XTR)
125 (RCV)
7 (XTR)
1 (RCV)
ISO3086
TTL
20
—
PROFIBUS
Half-Duplex
40 (XTR)
55 (RCV)
3 (XTR)
2 (RCV)
ISO1176
—
40
1
*Switching characteristics with V
CC1
= V
CC2
= 5 V.
25
Analog Applications Journal
2Q 2009
www.ti.com/aaj
High-Performance Analog Products
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