Tiny40.pdf

Features

• High Performance, Low Power AVR ® 8-Bit Microcontroller

• Advanced RISC Architecture

– 54 Powerful Instructions – Most Single Clock Cycle Execution

– 16 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 12 MIPS Throughput at 12 MHz

• Non-volatile Program and Data Memories

– 4K Bytes of In-System Programmable Flash Program Memory

– 256 Bytes Internal SRAM

– Flash Write/Erase Cycles: 10,000

– Data Retention: 20 Years at 85 o C / 100 Years at 25 o C

• Peripheral Features

– One 8-bit Timer/Counter with Two PWM Channels

– One 8/16-bit Timer/Counter

– 10-bit Analog to Digital Converter

• 12 Single-Ended Channels

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Master/Slave SPI Serial Interface

– Slave TWI Serial Interface

• Special Microcontroller Features

– In-System Programmable

– External and Internal Interrupt Sources

– Low Power Idle, ADC Noise Reduction, Stand-by and Power-down Modes

– Enhanced Power-on Reset Circuit

– Internal Calibrated Oscillator

• I/O and Packages

– 20-pin SOIC/TSSOP: 18 Programmable I/O Lines

– 20-pad VQFN/MLF: 18 Programmable I/O Lines

• Operating Voltage:

– 1.8 – 5.5V

• Programming Voltage:

–5V

• Speed Grade

– 0 – 4 MHz @ 1.8 – 5.5V

– 0 – 8 MHz @ 2.7 – 5.5V

– 0 – 12 MHz @ 4.5 – 5.5V

• Industrial Temperature Range

• Low Power Consumption

– Active Mode:

• 200 µA at 1 MHz and 1.8V

–Idle Mode:

• 25 µA at 1 MHz and 1.8V

– Power-down Mode:

• < 0.1 µA at 1.8V

8-bit

Microcontroller

with 4K Bytes

In-System

Programmable

Flash

ATtiny40

Preliminary

Rev. 8263A–AVR–08/10

1. Pin Configurations

Figure 1-1. Pinout of ATtiny40

SOIC/TSSOP

(PCINT8/ADC8) PB0

(PCINT7/ADC7) PA7

(PCINT6/ADC6) PA6

(PCINT5/ADC5/OC0B) PA5

(PCINT4/ADC4/T0) PA4

(PCINT3/ADC3) PA3

(PCINT2/ADC2/AIN1) PA2

(PCINT1/ADC1/AIN0) PA1

(PCINT0/ADC0) PA0

GND

PB1 (ADC9/PCINT9)

PB2 (ADC10/PCINT10)

PB3 (ADC11/ PC INT11)

PC0 (OC0A/SS/PCINT12)

PC1 (SCK/SCL/ICP1/T1/PCINT13)

PC2 (I NT0/CL KO/MISO/PCINT14)

PC3 (RESET/PCINT15)

PC4 (MOSI/SDA/TPIDATA/PCINT16)

PC5 (CLKI/TPICLK/PCINT17)

VCC

MLF/VQFN

(PCINT6/ADC6) PA6

(PCINT5/ADC5/OC0B) PA5

(PCINT4/ADC4/T0) PA4

(PCINT3/ADC3) PA3

(PCINT2/ADC2/AIN1) PA2

PC0 (OC0A/SS/PCINT12)

PC1 (SCK/SCL/ICP1/T1/PCINT13)

PC2 (I NT0/CL KO/MISO/PCINT14)

PC3 (RESET/PCINT15)

PC4 (MOSI/SDA/TPIDATA/PCINT16)

NOTE: Bottom pad should be soldered to ground.

1.1 Pin Description

1.1.1

VCC

Supply voltage.

1.1.2

GND

Ground.

1.1.3

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running and provided the reset pin has not been disabled. The min-

imum pulse length is given in Table 21-4 on page 168 . Shorter pulses are not guaranteed to

generate a reset.

The reset pin can also be used as a (weak) I/O pin.

ATtiny40

8263A–AVR–08/10

ATtiny40

1.1.4

Port A (PA7:PA0)

Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port A has alternate functions as analog inputs for the ADC, analog comparator and pin change

interrupt as described in “Alternate Port Functions” on page 52 .

1.1.5

Port B (PB3:PB0)

Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

The port also serves the functions of various special features of the ATtiny40, as listed on page

41 .

1.1.6

Port C (PC5:PC0)

Port C is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability except PC3 which has the RESET capability. To use pin PC3 as an I/O pin, instead of

RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port C pins that are externally pulled low

will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port C has alternate functions as analog inputs for the ADC, analog comparator and pin change

interrupt as described in “Alternate Port Functions” on page 52 .

The port also serves the functions of various special features of the ATtiny40, as listed on page

41 .

8263A–AVR–08/10

2. Overview

ATtiny40 is a low-power CMOS 8-bit microcontroller based on the compact AVR enhanced

RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny40

achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize

power consumption versus processing speed.

Figure 2-1. Block Diagram

V CC

RESET

PROGRAMMING

LOGIC

PROGRAM

COUNTER

INTERNAL

OSCILLATOR

CALIBRATED

OSCILLATOR

PROGRAM

FLASH

STACK

POINTER

WATCHDOG

TIMER

TIMING AND

CONTROL

INSTRUCTION

SRAM

RESET FLAG

INSTRUCTION

DECODER

INTERRUPT

UNIT

MCU STATUS

CONTROL

LINES

GENERAL

PURPOSE

REGISTERS

TIMER/

COUNTER0

TIMER/

COUNTER1

ALU

SPI

ANALOG

COMPARATOR

ISP

INTERFACE

STATUS

TWI

ADC

8-BIT DATA BUS

DATA REGISTER

PORT A

DIRECTION

REG. PORT A

DATA REGISTER

PORT B

DIRECTION

REG. PORT B

DATA REGISTER

PORT C

DIRECTION

REG. PORT C

DRIVERS

PORT A

DRIVERS

PORT B

DRIVERS

PORT C

PA[7:0]

PB[3:0]

PC[5:0]

GND

The AVR core combines a rich instruction set with 16 general purpose working registers and

system registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock cycle.

ATtiny40

8263A–AVR–08/10

ATtiny40

The resulting architecture is compact and code efficient while achieving throughputs up to ten

times faster than conventional CISC microcontrollers.

The ATtiny40 provides the following features: 4K bytes of In-System Programmable Flash, 256

bytes of SRAM, twelve general purpose I/O lines, 16 general purpose working registers, an 8-bit

Timer/Counter with two PWM channels, a 8/16-bit Timer/Counter, Internal and External Inter-

rupts, an eight-channel, 10-bit ADC, a programmable Watchdog Timer with internal oscillator, a

slave two-wire interface, a master/slave serial peripheral interface, an internal calibrated oscilla-

tor, and four software selectable power saving modes.

Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator,

and interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching

noise during ADC conversions by stopping the CPU and all I/O modules except the ADC. In

Power-down mode registers keep their contents and all chip functions are disabled until the next

interrupt or hardware reset. In Standby mode, the oscillator is running while the rest of the

device is sleeping, allowing very fast start-up combined with low power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The on-

chip, in-system programmable Flash allows program memory to be re-programmed in-system by

a conventional, non-volatile memory programmer.

The ATtiny40 AVR is supported by a suite of program and system development tools, including

macro assemblers and evaluation kits.

8263A–AVR–08/10

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika: