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Edited by Bill Travis

Circuit controls microneedle etching

Stephen Woodward, Marine Sciences, Chapel Hill, NC

A T ITS INVENTION roughly two dec-

pieces. If the etching current turns off

within milliseconds of the wire’s break-

ing, then the point of separation remains

supersharp. This sharp point is suitable

for use as a high-quality STM tip. Swift

interruption of the current, however, is

essential to tip sharpness, because only

a few milliseconds of overetch suffice to

dull and ruin the tip. The circuit in Fig-

ure 1 achieves precision etch-termina-

tion by using relay-actuated etch turn-

off based on the sudden drop in etch

current that occurs when the wire parts.

Precision sensing and full-wave rectifi-

cation of the etch current is critical to

circuit operation; the circuit achieves this

precision by using an unusual differen-

tial-input rectifier.

Precision, full-wave rectification of

low-level ac signals to a dc format is a

common signal-processing function;

many classic rectifier topologies accom-

ades ago, STM (scanning tunneling

microscopy) created a sensation be-

cause it was the first technology to make

atomic-scale-resolution imaging a rou-

tine procedure. An essential requirement

for the practical application of STM is

some means for the reproducible fabri-

cation of supersharp, atomic-scale needle

tips. One way to make the tips is to etch

them from short pieces of platinum wire

in a calcium-chloride electrolyte bath.

Applying an ac voltage between the elec-

trolyte and the wire generates a chemical

reaction accompanied by vigorous fizzing

at the surface of the liquid. This reaction

etches the platinum, causing the wire to

neck down and eventually break into two

Circuit controls

microneedle etching...................................... 87

Circuit removes

relay-contact bounce .................................... 88

Log-ratio amplifier has

six-decade dynamic range .......................... 90

VCXO makes inexpensive

dual-clock reference ...................................... 92

Publish your Design Idea in EDN . See the

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60 Hz AC

FROM VARIAC

OUT/IN

1N4004

FULL-WAVE

PRECISION RECTIFIER

RELAY: RS275-248

15V

120V AC

12V AC

STOP

470 µF

25V

START

1N914

~ 40 mA

7812

1N914

820

D 1

Figure 1

Q 3

2N4401

Q 1

2N3906

5.6k

IC 1A

12V

COMPARATOR

R 2

453*

0.3

R 1

10k*

THRESHOLD

SET: 0 TO 100

12V

100 µF

IC 1D

RUN

C 2

Q 2

2N3906

FILTER

IC 1B

10k

0.39

µF

D 2

10-TURN

+ DIAL

390k

IC 1C

1N914

C 1

47 µF

10V

10k

100k

NOTES:

ALL OP-AMPS ARE LM324s.

* = 1% METAL FILM.

100k*

0.22 µF

1 4

ETCH

CURRENT

This etch-control circuit produces supersharp microneedles by terminating the etching process at precisely the right time.

NOVEMBER 27, 2003 | EDN 87

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design

ideas

plish this function. But the accuracy of

typical precision rectifiers depends on the

precise matching of resistor ratios. More-

over, op-amp input-offset voltages limit

the accuracy of these standard circuits.

The offset error generally limits sensitiv-

ity to input spans no smaller than some

hundreds of millivolts. The converter in

this design avoids these faults and adds a

number of new and useful features. The

differential ac signal to be rectified goes

to the noninverting inputs of op amps

IC 1A and IC 1B ( Figure 1 ). Rectification

proceeds as follows: Consider a signal ex-

cursion, V IN , that drives IC 1A ’s input more

positive than IC 1B ’s. Amplifier IC 1A re-

sponds by driving diode D 1 into conduc-

tion, thereby forcing R 2 to track the in-

put. Amplifier IC 1B responds with a neg-

ative output excursion, forcing transistor

Q 2 to conduct sufficiently to cause the in-

verting input of IC 1A and the bottom end

of R 1 to track. Q 2 ’s emitter current, and,

therefore, collector current is then I

matching. Meanwhile, C 2 affords ac cou-

pling, which eliminates offset-voltage-re-

lated errors. Operation of the rest of the

etch controller is straightforward. IC 1C

implements a unity-gain, two-pole But-

terworth lowpass filter for good ripple at-

tenuation without excessive time delay.

Etching begins when you push the Start

pushbutton. The etch-current compara-

tor, IC 1D , then drives Q 3 to keep the relay

energized until the etch current drops be-

low the level set by the Threshold Set po-

tentiometer. IC 1D ’s output then drops

low, turning Q 3 off, opening the relay, and

terminating the etch. The result is a serv-

iceable, atomically sharp scan tip almost

every time.

V IN /R 2

V R1 /R 2 ;Q 2 is a high-alpha tran-

sistor.

The respective roles of the amplifiers

reverse for input excursions of the oppo-

site polarity, with D 2 and Q 2 conducting.

The match of Q 1 and Q 2 alpha values,

which is typically 0.3% or better, is the

only limit on rectification symmetry.

This precision rectifier is therefore

unique in that neither rectification sym-

metry nor common-mode rejection,

which exceeds 60 dB, depends on resistor

Circuit removes relay-contact bounce

John Guy, Maxim Integrated Products, Sunnyvale, CA

A DVANCES IN SEMICONDUCTOR tech-

drives the relay closed, and that relay clo-

sure connects the input of the hot-swap

circuitry to the power supply: 28V, in this

case. The hot-swap controller, IC 1 ,keeps

the p-channel MOSFET, Q 1 , off for a

minimum of 150 msec after the input

supply reaches a valid level.

That delay allows ample time

for contact bounce in the re-

lay to subside. After the 150-

msec delay, IC 1 drives

the MOSFET gate such

that the output voltage slews

at 9V/msec. This controlled

ramp rate minimizes the in-

rush current, thereby reduc-

ing stress on the power sup-

ply, the relay, and capacitors

downstream from the hot-

swap controller.

An example of relay con-

tact bounce shows three

bounces with an inrush-cur-

rent peak of almost 30A

( Figure 2 ). The top trace is output volt-

age at 10V/division, the lower trace is in-

put current at 5A/division, and the

output load is 54

nology have allowed ICs to replace

many mechanical relays, but relays

still dominate in high-current circuits

that must stand off high voltages of ar-

bitrary polarity. Contact bounce in those

10V/DIV

Q 1

MTD20P06

FROM

POWER SUPPLY

TO SYSTEM

POWER LOAD

K 1

28V

5A/DIV

OUT

100

SEC/DIV

The mechanical relay, K 1 ,by

itself exhibits contact bounce

on closure as shown.

Figure 2

R 1

100k

DRIVE

CIRCUIT

VS GATE

DRAIN

GND

PGOOD

IC 1

MAX5902

Figure 1

10V/DIV

GND

A hot-swap controller IC and external MOSFET removes con-

tact bounce from relay K 1 .

relays, however, can prove troublesome to

downstream circuitry. One approach to

contact bounce combines a relay with a

hot-swap controller. Such controllers are

increasingly popular as the means for

switching system components without

shutting down the system power. In Fig-

ure 1 , a relay contact replaces the pin of

a mechanical connector. The drive circuit

500 mA/DIV

1 mSEC/DIV

The Figure 1 circuit removes

relay-contact bounce and

reduces inrush current.

Figure 3

in parallel with

100

F. Use of the Figure 1 circuit under

these conditions yields a better picture

( Figure 3 ). The delayed rise in output

voltage is clearly visible, with no hiccups

arising from contact bounce. The input

current shows much less variation, peak-

ing under 1.5A before settling to a steady-

state value of 500 mA.

88 EDN | NOVEMBER 27, 2003

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design

ideas

Log-ratio amplifier has six-decade dynamic range

Reza Moghimi, Analog Devices, San Jose, CA

Y OU NEED OPTICAL-POWER monitor-

voltage or current; polarity; and scaling;

or operations such as log products and

ratios. Log-ratio amplifiers find applica-

tions in wide-dynamic-range ratiometric

measurements, which measure an un-

known signal against a variable-current

reference. The transfer function of the

circuit in Figure 1 is:

put range of the ADC sets the 4-mA full-

scale input-current range. Programming

I REF to a value of 40 to 600

ing to guarantee overall system per-

formance in fiber-optic communi-

cation systems. Logarithmic-signal pro-

cessing can maintain precise measure-

ments over a wide dynamic range. The

wide-dynamic-range signal undergoes

compression, and the use of a lower res-

olution measurement system then saves

cost. As an example of this technique,

consider a photodiode with responsivity

of 0.5A/W that converts light energy to a

current of 100 nA to 1 mA. With a four-

decade dynamic range and 1% error, the

required measurement resolution is

0.01

A places the

output in the middle of the measurement

range.

The components give an output-scale

factor of

1. This circuit has an output

defined over a range of 4.5 decades of

signal current, I IN , and 1.5 decades of ref-

erence current, I REF (limited by the load-

driving capability of the reference for a

total six-decade range. For most applica-

tions, you would use only a portion of the

entire six-decade range. By determining

the range of the expected input signals

and computing their ratios, you can use

the equations to predict the expected out-

put-voltage range. You can assign I REF and

I IN to match device performance to the

current range, but you should observe

polarity.

A log amplifier generally depends on

the nonlinear transfer function of a tran-

sistor. The general transfer function of a

log amplifier is related to I S and V T , which

both depend on temperature. I S

10 4 , or 1 ppm. This measurement

requires a 20-bit ADC. Instead, you can

compress this input to a 0 to 4V range us-

ing a log-ratio amplifier and then use a

10-bit ADC, substantially reducing the

system cost. Programming the reference

current allows shifting the output voltage

to the desired level. You can customize

and use the circuit in Figure 1 in appli-

cations involving unusual combinations

of dynamic range; input signal, such as

where K is the output scale factor, I IN is

the current that the photodiode gener-

ates, V T is a temperature-dependent term

(typically, 26 mV at 25

C and propor-

tional to absolute temperature), and I REF

is the reference current. V OUT

0 when

I IN

I REF . For proper operation, I IN /I REF

should always be greater than 0. The out-

put of the log-ratio circuit can be posi-

tive, negative, or bipolar, depending on

the ratio of I IN /I REF . The 4V full-scale in-

is the

50-k 33-TURN DIGITAL AD5201 POTENTIOMETER

DIGITAL TRIM FROM 3600 TO 50,000

330 pF

V CC

MAT02/AD

1C1

I IN

1/2 AD8626

V+

AD5201

LARGE-AREA

PHOTODIODE

SLEEP

OUT

V+

3600

I REF

GND

REF191

2.048V

REFERENCE

R 3

2.2k

V EE

1/2 AD8626

CS SDI

CLK

SHDN

330 pF

R 2

15.7k

V CC

10 µF

1 µF

R 1 (T)

TEMPERATURE

COMPENSATED

BAND-WIRE

SERIAL

INTERFACE

V RE

V IN

S CL

AD7810

MICRO-

PROCESSOR

D OU

V IN

Figure 1

AGN

CONV

This circuit is a programmable, temperature-compensated log-ratio amplifier.

90 EDN | NOVEMBER 27, 2003

www.edn.com

design

ideas

Figure 2

Figure 3

I REF =570

A, I IN =100 nA TO 4 mA.

I REF =40 A; I IN =100 nA TO 4 mA.

–10

–1

–30

–100

–300

–1k

–3k

–10k

–3

–10

–30

–100k

–300k

–1k

V (V65:OUT)

I (R86)/ I (V43)

V OUT has I REF programmed to full scale of 570

V OUT has I REF programmed to zero scale of 40

transistor’s collector saturation current,

and V T is the transistor’s “thermal volt-

age.” To overcome this temperature de-

pendency, this design uses a matched pair

of MAT02 transistors to cancel the I S

temperature drift and a temperature-

sensitive resistive voltage divider to com-

pensate for the temperature coefficient of

V T . The heart of the I REF generator is a

REF191. You adjust its output with an

AD5201 digital potentiometer. This

modification allows you to program the

reference current in 33 steps, from 40 to

600

capacitive loads in excess of 500 pF. Fig-

ures 2 and 3 show the transfer function

of the log-ratio amplifier at the input of

the ADC. The output is limited to 0 to 4V

to match the unipolar input-voltage

range of the AD7810 ADC.

The combination of the REF191 and

the AD5201 provides a current source

that is stable with respect to time and

temperature. For higher resolution, you

can use the 1024-position AD5231. The

AD8626 is a dual precision-JFET-input

amplifier with true single-supply opera-

tion to 26V, low power consumption, and

rail-to-rail output swing, allowing a wide

dynamic range. Its output is stable with

REFERENCE

1. Sheingold, Dan, Editor, Nonlinear

Circuits

Handbook ,

Analog Devices,

ISBN: 0-916550-01-X.

VCXO makes inexpensive dual-clock reference

Said Jackson, Equator Technologies Inc, Campbell, CA

T HIS DESIGN IDEA describes an inex-

and a wider VCXO pull range than com-

parable monolithic approaches at less

than one-third of their cost.

You can use the circuit in a wide vari-

ety of applications; the indicated com-

ponent values make it a perfect fit for a

digital audio/video system, such as a dig-

ital video recorder, digital camera, or set-

top box. The circuit is well-suited to sin-

gle-chip, media-processing applications

that require adjustability, low cost, and

low-jitter performance, such as systems

based on Equator’s (www.equator.com)

broadband-signal processors. These

types of systems generally require a fixed

frequency, such as 25 or 33 MHz, for the

processor subsystem (Ethernet, PCI bus,

for example) and an adjustable 27-MHz

reference clock for the audio/video refer-

ence subsystem. A PLL system generally

controls the 27-MHz reference clock.

(This PLL is usually implemented in soft-

ware with PWM outputs from the mi-

croprocessor controlling the 27-MHz

clock’s deviation.) This approach guar-

antees a correct synchronization of the

audio and the video data streams to each

other and the broadcast source. The clock

requires

pensive circuit to generate two ex-

tremely high-quality, crystal-clock-

reference-signals, one of which is a

PWM-controlled VCXO (voltage-con-

trolled crystal oscillator) clock signal

( Figure 1 ). The design also includes cir-

cuitry to statically switch and hold the

VCXO at its nominal fixed frequency of

operation (equivalent to 50% PWM)

without requiring any external PWM

stimulus. Most digital audio/video mi-

croprocessor-based systems today require

several independent clocks with low jit-

ter and the potential adjustability a

VCXO provides. The described circuit re-

places two expensive monolithic VCXO

and crystal oscillators at a fraction of

their cost and provides much higher

quality output signals than the mono-

lithic solutions can generate, especially at

the control limits of the VCXO (

50-ppm adjustability, and the

circuit in Figure 1 provides more than

70 ppm. The circuit suits high-volume

manufacturing, the highest quality signal

(lowest jitter), and the lowest production

cost.

The design incorporates several novel

circuit features, such as both overtone-

and harmonic-crystal operation, use of

inexpensive voltage-controlled capacitors

(varactor diodes), a single 3.3V power-

supply operating voltage, and a selectable

50%-duty-cycle, 27-MHz-operation,

fixed-frequency mode. The fixed-fre-

quency mode allows operation at 27

MHz without the PLL-PWM circuit’s

having to provide a 50% duty cycle, po-

tentially freeing up hardware and soft-

ware resources in the microprocessor that

usually generates the PWM signal. This

mode is usually invoked when the au-

dio/video signals are generated internal-

100%

deviation). The circuit generates signals

with higher stability, much lower jitter,

lower operating voltage (3.3 versus 5V)

92 EDN | NOVEMBER 27, 2003

www.edn.com

design

ideas

32-MHz,

THIRD-OVERTONE

FOXSD/320-20

Y 1

C 1

1000 pF

C 2

10 pF

C 3

10 pF

AUDIO/VIDEO VCXO

R 3

560

EPCOS B82494-A1472-K

R 5

L 1

R 6

IC 3B

74LVC04

R 1

REF_27 MHz

R 7

560

IC 1A

74LVC04

IC 1B

74LVC04

IC 3A

74LVC04

REF_32 MHz

3.3V

20-PPM, 18 pF-LOAD,

27-MHz CRYSTAL SMD

CITIZEN

HCM49-27.000MDDUT

TSSOP14

74LVC00APWDH

R 4

3.3

TSSOP14

74LVC00APWDH

Y 2

32 MHz

IC 2A

IC 2B

Figure 1

R 8

3.3k

R 9

3.3k

CONTROL

VOLTAGE

PWM

SIGNAL

C 4

C 5

0.1

10V

IC 2C

C 6

0.01

C 7

0.01

C 8

0.01

R 10

47k

R 11

47k

C 9

TSSOP14

74LVC00APWDH

FIXED_VS_

VCXO_SELECT

D 2

BB133

PHILIPS

IC 2D

D 1

BB133

PHILIPS

C 11

0.01

C 10

3.3 pF

TSSOP14

74LVC00APWDH

PWM_INPUT

PWM FROM

PLL PHASE

COMPARATOR

PWM MULTIPLEXER

This circuit, ideal for A/V applications, generates two high-quality clock-reference signals.

ly to the system, such as when playing

back from a hard drive, and audio/video

synchronization to an external source is

unnecessary.

The circuit includes IC 1 , a 32-MHz,

PCI-based fixed-frequency reference

clock; IC 2 , a PWM multiplexer; and IC 3 ,

a 27-MHz VCXO clock. A Fox (www.fox

online.com) 32-MHz, third-overtone

crystal serves to generate both the PCI

reference clock and the 50%-duty-cycle

reference for the fixed-frequency mode.

A third-overtone, 32-MHz part is less ex-

pensive and more mechanically robust

than a 33-MHz, fundamental-mode

crystal at the expense of running the PCI

clock slightly slower. The tank circuit

around inductor L 1 and capacitors C 1 and

C 3 prevent the crystal from oscillating at

its fundamental mode of approximately

11 MHz. This tank circuit works by cre-

ating an LC series-resonant circuit be-

tween L 1 and C 3 that has natural reso-

nance at approximately 24 MHz, which

is approximately 75% of the desired 32-

MHz frequency. Note that C 1 is large

enough to have no effect on this tank cir-

cuit’s resonance frequency; it merely acts

as a dc blocker for inductor L 1 . One thing

to avoid is to connect this tank circuit to

the input side of inverter IC 1A . Connect-

ing it to the input side of IC 1A could po-

tentially create a resonant RC circuit with

resistor R 1 and capacitor C 1 acting as the

RC components. This circuit could os-

cillate at less than 1 kHz, a frequency at

which L 1 would effectively be a short cir-

cuit, and crystal Y 1 would be an open cir-

cuit. Placing C 1 and L 1 on the output side

of IC 1A prevents this spurious-oscillation

mode.

By tuning L 1 and C 3 , you can adjust the

circuit to oscillate at a frequency higher

than the third overtone. Oscillation at the

fifth, seventh, or even ninth overtone is

possible and is limited only by the per-

formance of IC 1A and the parasitic ca-

pacitance. The 32-MHz PCI reference-

clock output also serves as a 50%-

duty-cycle reference for the VCXO when

the VCXO is operating in its fixed-fre-

quency, 27-MHz mode. Multiplexer IC 2

selects either this 32-MHz, 50% PWM

clock signal or the PWM clock signal

from a PLL phase comparator (usually

implemented in the microprocessor and

not shown in the schematic) to set the

VCXO to its fixed-frequency mode. The

advantage of using the PCI clock for this

feature is that traditional circuits would

have to generate an analog one-half-V DD

voltage and use an analog multiplexer to

set the VCXO at its nominal frequency.

Thus, this design avoids the necessity of

using accurate and expensive analog cir-

cuitry and also generates a reference sig-

nal with much higher immunity to tem-

perature,

for example,

than analog

approaches could provide.

Digital multiplexer IC 2 forwards one

of two PWM signals to the VCXO based

on the state of the fixed-versus-VCXO se-

lected input signal. The PWM-input sig-

nal serves as the PWM reference input to

the VCXO if the select pin is high, and the

design uses the 50%-duty-cycle PWM

signal from the PCI clock circuit if the se-

lect pin is low. The design uses a 74LVC00

chip as a multiplexer because of its ready

availability and low cost. IC 2C buffers the

PWM signal, and the cascaded RC filter

comprising R 8 ,R 9 ,C 8 , and C 9 then low-

pass-filters the signal. The analog-voltage

stability of the VCXO control voltage at

the output of this RC filter depends on

the quality of the V DD supply to IC 2C .IC 2

receives its 3.3V power through an RC fil-

ter: R 4 with C 4 and C 5 .IC 2 with R 8 ,R 9 ,C 8 ,

and C 9 thus form a highly accurate D/A

converter.

94 EDN | NOVEMBER 27, 2003

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