Programming_Embedded_System_II.pdf

(2310 KB) Pobierz
Microsoft Word - PES II guide.
1
2
3
4
5
6
7
P1.0
VCC
40
39
38
37
36
35
34
P1.1
P0.0
P1.2
P1.3
P0.1
P0.2
P1.4
P0.3
P1.5
P0.4
P1.6
P0.5
8
9
10
P1.7
RST
P0.6
P0.7
33
32
31
30
29
28
27
26
25
24
P3.0
/ EA
11
12
13
14
15
16
17
18
19
20
P3.1
ALE
P3.2
/ PSEN
P3.3
P3.4
P2.7
P2.6
P3.5
P2.5
P3.6
P2.4
P3.7
P2.3
XTL2
XTL1
P2.2
P2.1
23
22
21
VSS
P2.0
377115002.003.png
Copyright © Michael J. Pont, 2002-2003
This document may be freely distributed and copied, provided that copyright notice at
the foot of each OHP page is clearly visible in all copies.
II
377115002.004.png 377115002.005.png
Seminar 1: A flexible scheduler for single-processor embedded systems
1
Overview of this seminar
2
Overview of this course
3
By the end of the course you’ll be able to …
4
Main course text
5
IMPORTANT: Course prerequisites
6
Review: Why use C?
7
Review: The 8051 microcontroller
8
Review: The “super loop” software architecture
9
Review: An introduction to schedulers
10
Review: Building a scheduler
11
Overview of this seminar
12
The Co-operative Scheduler
13
Overview
14
The scheduler data structure and task array
15
The size of the task array
16
One possible initialisation function:
17
IMPORTANT: The ‘one interrupt per microcontroller’ rule!
18
The ‘Update’ function
19
The ‘Add Task’ function
20
The ‘Dispatcher’
22
Function arguments
24
Function pointers and Keil linker options
25
The ‘Start’ function
28
The ‘Delete Task’ function
29
Reducing power consumption
30
Reporting errors
31
Displaying error codes
34
Hardware resource implications
35
What is the CPU load of the scheduler?
36
Determining the required tick interval
38
Guidelines for predictable and reliable scheduling
40
Overall strengths and weaknesses of the scheduler
41
Preparations for the next seminar
42
III
377115002.006.png
Seminar 2: A closer look at co-operative task scheduling (and some alternatives)
43
Overview of this seminar
44
Review: Co-operative scheduling
45
The pre-emptive scheduler
46
Why do we avoid pre-emptive schedulers in this course?
47
Why is a co-operative scheduler (generally) more reliable?
48
Critical sections of code
49
How do we deal with critical sections in a pre-emptive system?
50
Building a “lock” mechanism
51
The “best of both worlds” - a hybrid scheduler
55
Creating a hybrid scheduler
56
The ‘Update’ function for a hybrid scheduler.
58
Reliability and safety issues
61
The safest way to use the hybrid scheduler
63
Other forms of co-operative scheduler
65
PATTERN: 255-T ICK S CHEDULER
66
PATTERN: O NE -T ASK S CHEDULER
67
PATTERN: O NE -Y EAR S CHEDULER
68
PATTERN: S TABLE S CHEDULER
69
Mix and match …
70
Preparations for the next seminar
71
IV
377115002.001.png
Seminar 3: Shared-clock schedulers for multi-processor systems
73
Overview of this seminar
74
Why use more than one processor?
75
Additional CPU performance and hardware facilities
76
The benefits of modular design
78
The benefits of modular design
79
So - how do we link more than one processor?
80
Synchronising the clocks
81
Synchronising the clocks
82
Synchronising the clocks - Slave nodes
83
Transferring data
84
Transferring data (Master to Slave)
85
Transferring data (Slave to Master)
86
Transferring data (Slave to Master)
87
Detecting network and node errors
88
Detecting errors in the Slave(s)
89
Detecting errors in the Master
90
Handling errors detected by the Slave
91
Handling errors detected by the Master
92
Enter a safe state and shut down the network
93
Reset the network
94
Engage a backup Slave
95
Why additional processors may not improve reliability
96
Redundant networks do not guarantee increased reliability
97
Replacing the human operator - implications
98
Are multi-processor designs ever safe?
99
Preparations for the next seminar
100
V
377115002.002.png
Zgłoś jeśli naruszono regulamin