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I2C manual
INTEGRATED CIRCUITS
AN10216-01 I
2 C Manual
APPLICATION NOTE
AN10216-01
I 2 C MANUAL
Abstract – The I 2 C Manual provides a broad overview of the various serial buses,
why the I 2 C bus should be considered, technical detail of the I 2 C bus and how it
works, previous limitations/solutions, comparison to the SMBus, Intelligent Platform
Management Interface implementations, review of the different I 2 C devices that are
available and patent/royalty information. The I 2 C Manual was presented during the 3
hour TecForum at DesignCon 2003 in San Jose, CA on 27 January 2003.
Jean-Marc Irazabal – I 2 C Technical Marketing Manager
Steve Blozis – I 2 C International Product Manager
Specialty Logic Product Line
Logic Product Group
Philips Semiconductors March 24, 2003
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AN10216-01 I 2 C Manual
TABLE OF CONTENTS
2
AN10216-01 I 2 C Manual
3
AN10216-01 I 2 C Manual
OVERVIEW
Description
Philips Semiconductors developed the I 2 C bus over 20 years ago and has an extensive collection of specific use and
general purpose devices. This application note was developed from the 3 hour long I 2 C Overview TecForum presentation
at DesignCon 2003 in San Jose, CA on 27 January 2003 and provides a broad overview of how the I 2 C bus compares to
other serial buses, how the I 2 C bus works, ways to overcome previous limitations, new uses of I 2 C such as in the
Intelligent Platform Management Interface, overview of the various different categories of I 2 C devices and patent/royalty
information. Full size Slides are posted as a PDF file on the Philips Logic I 2 C collateral web site as DesignCon 2003
TecForum I 2 C Bus Overview PDF file. Place holder and title slides have been removed from this application note and
some slides with all text have been incorporated into the application note speaker notes.
Serial Bus Overview
three shared signal lines, for bit timing, data, and R/W.
The selection of communicating partners is made with
one separate wire for each chip. As the number of chips
grows, so do the selection wires. The next stage is to
use multiplexing of the selection wires and call them an
address bus.
IEEE1394
If there are 8 address wires we can select any one of
256 devices by using a ‘one of 256’ decoder IC. In a
parallel bus system there could be 8 or 16 (or more)
data wires. Taken to the next step, we can share the
function of the wires between addresses and data but it
starts to take quite a bit of hardware and worst is, we
still have lots of wires. We can take a different
approach and try to eliminate all except the data wiring
itself. Then we need to multiplex the data, the selection
(address), and the direction info - read/write. We need
to develop relatively complex rules for that, but we save
on those wires. This presentation covers buses that use
only one or two data lines so that they are still attractive
for sending data over reasonable distances - at least a
few meters, but perhaps even km.
SERIAL
BUSES
UART
SPI
B U S
DesignCon 2003 TecForum I 2 C Bus Overview
5
Slide 5
General concept for Serial communications
SCL
SDA
Typical Signaling Characteristics
select 3
select 2
select 1
READ
or
WRITE?
enable
Shift Reg#
enable
Shift Reg#
enable
Shift Reg#
// to Ser.
// to Ser.
// to Ser.
R/W
R/W
R/W
DATA
“MASTER”
SLAVE 1
SLAVE 2
SLAVE 3
LVTTL
• A point to point communication does not require a Select control signal
RS422/485
I 2 C
• An asynchronous communication does not have a Clock signal
I 2 C
S MBu s
• Data, Select and R/W signals can share the same line, depending on the protocol
PECL
LV PE CL LVDS
I 2 C
1394
• Notice that Slave 1 cannot communicate with Slave 2 or 3 (except via the ‘master’)
Only the ‘master’ can start communicating. Slaves can ‘only speak when spoken to’
GTL+
DesignCon 2003 TecForum I 2 C Bus Overview
6
CML
LVT
LVC
5 V
3.3 V
2.5 V
GTL
GTLP
Slide 6
DesignCon 2003 TecForum I 2 C Bus Overview
7
Buses come in two forms, serial and parallel. The data
and/or addresses can be sent over 1 wire, bit after bit, or
over 8 or 32 wires at once. Always there has to be some
way to share the common wiring, some rules, and some
synchronization. Slide 6 shows a serial data bus with
Slide 7
Devices can communicate differentially or single ended
with various signal characteristics as shown in Slide 7.
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AN10216-01 I 2 C Manual
also because it may be used within the PC software as a
general data path that USB drivers can use.
Transmission Standards
Terminology for USB: The use of older terms such as
the spec version 1.1 and 2.0 is now discouraged. There
is just “USB” (meaning the original 12 Mbits/sec and
1.5 Mbits/sec speeds of USB version 1.1) and Hi-Speed
USB meaning the faster 480 Mbits/sec option included
in spec version 2.0. Parts conforming to or capable of
the 480 Mbits/sec are certified as Hi-Speed USB and
will then feature the logo with the red stripe “Hi-Speed”
fitted above the standard USB logo. The reason to avoid
use of the new spec version 2.0 as a generic name is
that this version includes all the older versions and
speeds as well as the new Hi-Speed specs. So USB 2.0
compliance does NOT imply Hi-Speed (480 Mbits/sec).
ICs can be compliant with USB 2.0 specifications yet
only be capable of the older ‘full speed’ or 12
Mbits/sec.
2500
655
CML
400
GTLP
BTL
ETL
1394.a
35
10
General
Purpose
Logic
1
RS-422
RS-485
0.1
I 2 C
RS-232
RS-423
0.5
0
10
100
1000
Backplane Length (meters)
Cable Length (meters)
DesignCon 2003 TecForum I 2 C Bus Overview
8
Slide 8
The various data transmission rates vs length or cable
or backplane length of the different transmission
standards are shown in Slide 8.
Bus characteristics compared
Bu s
Data rat e
(bits / sec)
Length
(meters)
Length limiting f actor
Nodes
Typ.number
Node number
limiting f actor
Speed of various connectivity methods (bits/sec)
I 2 C
400k
2
w iring capacitance
20
400pF max
I 2 C w ith buf fer
400k
100
propagation delays
an y
no limit
I 2 C high speed
3.4M
0.5
w iring capacitance
5
100pF max
CAN 1 w ire
33k
100
total capacitance
32
load resistance and
transceiver current
drive
CAN (1 Wire)
33 kHz (typ)
5k
10km
I 2 C (‘Industrial’, and SMBus)
SPI
CA N diff erential
125k
500
propagation delays
100
100 kHz
110 kHz (original speed)
1M
4 0
US B (low -speed, 1.1)
1.5M
3
cable specs
2
bus specs
CAN (fault tolerant)
125 kHz
USB (full -speed, 1.1)
1.5/12M
5 cables linking 6 nodes
(5m cable node to node)
bus and hub specs
25
127
I 2 C
400 kHz
Hi - Sp e e d US B (2.0)
480M
IEEE-1394
100 to 400M+
72
16 hops, 4.5M each
63
6-bit address
CAN (high speed)
1 MHz
I 2 C ‘High Speed mode’
3.4 MHz
USB (1.1)
1.5 MHz or 12 MHz
SCSI (parallel bus)
40 MHz
Fast SCSI
8-80 MHz
Ultra SCSI-3
18-160 MHz
Firewire / IEEE1394
400 MHz
DesignCon 2003 TecForum I 2 C Bus Overview
10
Hi-Speed USB (2.0)
480 MHz
Slide 10
DesignCon 2003 TecForum I 2 C Bus Overview
9
Slide 9
In Slide 10 we look at three important characteristics:
• Speed, or data rate
• Number of devices allowed to be connected (to
share the bus wires)
• Total length of the wiring
Increasing fast serial transmission specifications are
shown in Slide 9. Proper treatment of the 480 MHz
version of USB - trying to beat the emerging 400 MHz
1394a spec - that is looking to an improved ‘b’ spec - -
etc is beyond the scope of this presentation. Philips is
developing leading-edge components to support both
USB and 1394 buses.
Numbers are supposed to be realistic estimates but are
based on meeting bus specifications. But rules are made
to be broken! When buffered, I 2 C can be limited by
wiring propagation delays but it is still possible to run
much longer distances by using slower clock rates and
maybe also compromising the bus rise and fall-time
specifications on the buffered bus because it is not
bound to conform to I 2 C specifications.
Today the path forward in USB is built on “OTG” (On
The Go) applications but the costs and complexity of
this are probably beyond the limits of many customers.
If designers are identified as designing for large
international markets then please contact the USB
group for additional support, particularly of Host and
OTG solutions. Apologies for inclusion of the parallel
SCSI bus. It is intended for comparison purposes and
The figure in Slide 10 limiting I 2 C range by
propagation delays is conservative and allows for
published response delays in chips like older E 2
memories. Measured chip responses are typically <
700 ns and that allows for long cable delays and/or
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