2764.PDF

M2764A

NMOS 64K (8K x 8) UV EPROM

FAST ACCESS TIME: 180ns

EXTENDED TEMPERATURE RANGE

SINGLE 5V SUPPLY VOLTAGE

LOW STANDBY CURRENT: 35mA max

TTL COMPATIBLE DURING READ and PROGRAM

FAST PROGRAMMING ALGORITHM

ELECTRONIC SIGNATURE

FDIP28W (F)

PROGRAMMING VOLTAGE: 12V

DESCRIPTION

The M2764A is a 65,536 bit UV erasable and

electrically programmable memory EPROM. It is

organized as 8,192 words by 8 bits.

The M27C64A is housed in a 28 pin Window Ce-

ramic Frit-Seal Dual-in-Line package. The trans-

parent lid allows the user to expose the chip to

ultraviolet light to erase the bit pattern. A new

pattern can then be written to the device by follow-

ing the programming procedure.

Figure 1. Logic Diagram

V CC

V PP

A0-A12

Q0-Q7

Table 1. Signal Names

M2764A

A0 - A12

Address Inputs

Q0 - Q7

Data Outputs

Chip Enable

Output Enable

V SS

Program

AI00776B

V PP

Program Supply

V CC

Supply Voltage

V SS

Ground

March 1995

1/10

M2764A

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

T A

Ambient Operating Temperature

grade 1

grade 6

0 to 70

–40 to 85

T BIAS

Temperature Under Bias

grade 1

grade 6

–10 to 80

–50 to 95

V IO Input or Output Voltages –0.6 to 6.5 V

V CC Supply Voltage –0.6 to 6.5 V

V A9 A9 Voltage –0.6 to 13.5 V

V PP Program Supply –0.6 to 14 V

Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause

permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those

indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods

may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.

T STG

Storage Temperature

–65 to 125

Figure 2. DIP Pin Connections

Read Mode

The M2764A has two control functions, both of

which must be logically satisfied i n o rder to obtain

data at the outputs. Chip Enable (E) is the power

control and sh ou ld be used for device selection.

Output Enable (G) is the output control and should

be used to gate data to the output pins, inde-

pendent of device selection.

Assuming that the addresses are stable, add re ss

access time (t AVQV ) is equal to the delay from E to

output (t ELQV ). Da ta is available at t he outputs after

the falling edge of G, assuming that E has been low

and the addresses have been stable for at least

t AVQV -t GLQV .

Standby Mode

The M2764A has a standby mode which reduces

the maximum active power current from 75mA to

35mA. The M2764A is placed in the st andby mode

by applying a TTL high signal to the E input. When

in the standby mode, the outputs a re in a high

impedance state, independent of the G input.

Two Line Output Control

Because EPROMs are usually used in larger mem-

ory arrays, the product features a 2 line control

function which accommodates the use of multiple

memory connection. The two line control function

allows :

a. the lowest possible memory power dissipation,

b. complete assurance that output bus contention

will not occur.

V PP

V CC

A12

A11

M2764A

A10

V SS

AI00777

Warning: NC = Not Connected.

DEVICE OPERATION

The seven modes of operations of the M2764A are

listed in the Operating Modes table. A single 5V

power supply is required in the read mode. All

inputs are TTL levels except for V PP and 12V on A9

for Electronic Signature.

2/10

M2764A

DEVICE OPERATION (cont’d)

of low inherent inductance and should be placed

as close to the device as possible. In addition, a

4.7 m F bulk electrolytic capacitor should be used

between V CC and V SS for every eight devices. The

bulk capacitor should be located near the power

supply connection point. The purpose of the bulk

capacitor is to overcome the voltage drop caused

by the inductive effects of PCB traces.

Programming

When delivered (and after each erasure for UV

EPROM), all bits of the M2764A are in the “1" state.

Data is introduced by selectively programming ”0s"

into the desired bit locations. Although only “0s” will

be programmed, both “1s” and “0s” can be present

in the data word. The only way to change a “0" to

a ”1" is by ultraviolet light erasure.

The M2764A is in the pr og ram mi ng mode when

V PP input is at 12.5V and E and P are at TTL low.

The data to be programmed is applied, 8 bits in

parallel, to the data output pins. The levels required

for the address and data inputs are TTL.

Fast Programming Algorithm

Fast Programming Algorithm rapidly programs

M2764A EPROMs using an efficient and reliable

method suited to the production programming en-

vironment. Programming reliability is also ensured

as the incremental program margin of each byte is

continually monitored to determine when it has

F or the most efficient use of these two control lines,

E should be decoded and us ed as the primary

device selecting function, while G should be made

a common connectio n to all devices in the array

and connected to the READ line from the system

control bus.

This ensures that all deselected memory devices

are in their low power standby mode and that the

output pins are only active when data is desired

from a particular memory device.

System Considerations

The power switching characteristics of fast

EPROMs require careful decoupling of the devices.

The supply current, I CC , has three segments that

are of interest to the system designer: the standby

current level, the active current level, and transient

current peaks t ha t are produced by the falling and

rising edges of E. The magnitude of the transient

current peaks is dependent on the capacitive and

inductive loading of the device at the output. The

associated transient voltage peaks can be sup-

pressed by complying with the two line output

control and by properly selected decoupling ca-

pacitors. It is recommended that a 1 m F ceramic

capacitor be used on every device between V CC

and V SS . This should be a high frequency capacitor

Table 3. Operating Modes

Mode

V PP

Q0 - Q7

Read

V IL

V IH

V CC

Data Out

Output Disable

V IL

V IH

V CC

Hi-Z

Program

V IL

V IH

V IL Pulse

V PP

Data In

Verify

V IL

V IH

V PP

Data Out

Program Inhibit

V IH

V PP

Hi-Z

Standby

V IH

V CC

Hi-Z

Electronic Signature

V IL

V IH

V ID

V CC

Codes Out

Note: X = V IH or V IL , V ID = 12V

0.5%.

Table 4. Electronic Signature

Identifier

Hex Data

Manufacturer’s Code

V IL

20h

Device Code

V IH

08h

3/10

M2764A

AC MEASUREMENT CONDITIONS

Figure 4. AC Testing Load Circuit

20ns

Input Pulse Voltages 0.45V to 2.4V

Input and Output Timing Ref. Voltages 0.8V to 2.0V

1.3V

1N914

Note that Output Hi-Z is defined as the point where data

is no longer driven.

Figure 3. AC Testing Input Output Waveforms

3.3k

DEVICE

UNDER

TEST

OUT

2.4V

2.0V

C L = 100pF

0.45V

0.8V

AI00827

C L includes JIG capacitance

AI00828

Table 5. Capacitance (1) (T A = 25 ° C, f = 1 MHz )

Symbol

Parameter

Test Condition

Min

Max

Unit

C IN

Input Capacitance

V IN = 0V

C OUT

Output Capacitance

V OUT = 0V

Note: 1. Sampled only, not 100% tested.

Figure 5. Read Mode AC Waveforms

A0-A12

VALID

tAVQV

tAXQX

tGLQV

tEHQZ

tELQV

tGHQZ

Q0-Q7

DATA OUT

Hi-Z

AI00778

4/10

Input Rise and Fall Times

M2764A

Table 6. Read Mode DC Characteristics (1)

(T A = 0 to 70

C or –40 to 85

C; V CC = 5V

5% or 5V

10%; V PP = V CC )

Symbol

Parameter

Test Condition

Min

Max

Unit

I LI

Input Leakage Current

V IN

V CC

I LO

Output Leakage Current

V OUT = V CC

I CC

Supply Current

E = V IL , G = V IL

I CC1

Supply Current (Standby)

E = V IH

I PP

Program Current

V PP = V CC

V IL

Input Low Voltage

–0.1

0.8

V IH

Input High Voltage

V CC + 1

V OL

Output Low Voltage

I OL = 2.1mA

0.45

V OH

Output High Voltage

I OH = –400

2.4

Note: 1. V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP .

Table 7A. Read Mode AC Characteristics (1)

(T A = 0 to 70 ° C or –40 to 85 ° C; V CC = 5V ± 5% or 5V ± 10%; V PP = V CC )

Test

Condition

M2764A

Symbol Alt

Parameter

-1

-2, -20

blank, -25

Unit

Min

Max

Min

Max

Min

Max

t AV QV

t ACC

Address Valid to

Output Valid

E = V IL ,

G = V IL

180

200

250

t ELQV

t CE

Chip Enable Low

to Output Valid

G = V IL

180

200

250

t GLQV

t OE

Output Enable

Low to Output Valid

E = V IL

100

t EHQZ (2)

t DF

Chip Enable High

to Output Hi-Z

G = V IL

t GHQZ (2)

t DF

Output Enable

High to Output Hi-Z

E = V IL

t AXQX

t OH

Address Transition

to Output Transition

E = V IL ,

G = V IL

Table 7B. Read Mode AC Characteristics (1)

(T A = 0 to 70 ° C or –40 to 85 ° C; V CC = 5V ± 5% or 5V ± 10%; V PP = V CC )

Test

Condition

M2764A

Symbol Alt

Parameter

-3

-4

Unit

Min

Max

Min

Max

t AV QV

t ACC

Address Valid to

Output Valid

E = V IL ,

G = V IL

300

450

t ELQV

t CE

Chip Enable Low

to Output Valid

G = V IL

300

450

t GLQV

t OE

Output Enable

Low to Output Valid

E = V IL ,

120

150

t EHQZ (2)

t DF

Chip Enable High

to Output Hi-Z

G = V IL

105

130

t GHQZ (2)

t DF

Output Enable

High to Output Hi-Z

E = V IL

105

130

t AXQX

t OH

Address Transition

to Output Transition

E = V IL ,

G = V IL

Notes: 1. V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP .

2. Sampled only, not 100% tested.

5/10

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