24C64.pdf

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M24C64
M24C32
64Kbit and 32Kbit Serial I²C Bus EEPROM
FEATURES SUMMARY
Two-Wire I 2 C Serial Interface
Supports 400kHz Protocol
Figure 1. Packages
Single Supply Voltage:
– 4.5 to 5.5V for M24Cxx
– 2.5 to 5.5V for M24Cxx-W
– 1.8 to 5.5V for M24Cxx-R
Write Control Input
BYTE and PAGE WRITE (up to 32 Bytes)
8
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
1
Automatic Address Incrementing
Enhanced ESD/Latch-Up Protection
PDIP8 (BN)
More than 1 Million Erase/Write Cycles
More than 40-Year Data Retention
8
1
SO8 (MN)
150 mil width
Table 1. Product List
Reference
Part Number
M24C64
M24C64
M24C64-W
M24C64-R
TSSOP8 (DW)
169 mil width
M24C32
M24C32
M24C32-W
M24C32-R
UFDFPN8 (MB)
2x3mm² (MLP)
January 2005
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M24C64, M24C32
TABLE OF CONTENTS
Write Control ( WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Maximum R L Value versus Bus Capacitance (C BUS ) for an I 2 C Bus . . . . . . . . . . . . . . . . 5
Figure 5. I 2 C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. Write Mode Sequences with WC=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Write Mode Sequences with WC=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . 10
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M24C64, M24C32
Table 13. DC Characteristics (M24Cxx (1) , M24Cxx-W6 and M24Cxx-W3) . . . . . . . . . . . . . . . . . . . 16
Table 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 21. UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm,
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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M24C64, M24C32
SUMMARY DESCRIPTION
These I 2 C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 8192 x 8 bits (M24C64) and 4096 x 8 bits
(M24C32).
Table 2. Signal Names
E0, E1, E2
Chip Enable
SDA
Serial Data
Figure 2. Logic Diagram
SCL
Serial Clock
V CC
WC
Write Control
V CC
Supply Voltage
3
V SS
Ground
Power On Reset: V CC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. At Power-up, the
internal reset is held active until V CC has reached
the Power On Reset (POR) threshold voltage, and
all operations are disabled – the device will not re-
spond to any command. In the same way, when
V CC drops from the operating voltage, below the
Power On Reset (POR) threshold voltage, all op-
erations are disabled and the device will not re-
spond to any command.
A stable and valid V CC (as defined in Table 9. and
Table 10. ) must be applied before applying any
logic signal.
E0-E2
SDA
SCL
M24C64
M24C32
WC
V SS
AI01844B
I 2 C uses a two-wire serial interface, comprising a
bi-directional data line and a clock line. The devic-
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I 2 C bus definition.
The device behaves as a slave in the I 2 C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is foll owed by a Device
Select Code and Read/Write bit (RW) (as de-
scribed in Table 3. ), terminated by an acknowl-
edge bit.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9 th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Figure 3. DIP, SO, TSSOP and UFDFPN
Connections
M24C64
M24C32
E0
1
2
3
4
8
7
6
5
V CC
E1
WC
E2
SCL
V SS
SDA
AI01845C
Note: See PACKAGE MECHANICAL section for package dimen-
sions, and how to identify pin-1.
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M24C64, M24C32
SIGNAL DESCRIPTION
Serial Clock (SCL). This input signal is used to
strobe all data in and out of the device. In applica-
tions where this signal is used by slave devices to
synchronize the bus to a slower clock, the bus
master must have an open drain output, and a
pull-up resistor must be connected from Serial
Clock (SCL) to V CC . ( Figure 4. indicates how the
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the bus master
has a push-pull (rather than open drain) output.
Serial Data (SDA). This bi-directional signal is
used to transfer data in or out of the device. It is an
open drain output that may be wire-OR’ed with
other open drain or open collector signals on the
bus. A pull up resistor must be connected from Se-
rial Data (SDA) to V CC . ( Figure 4. indicates how
the value of the pull-up resistor can be calculated).
Chip Enable (E0, E1, E2). These input signals
are used to set the value that is to be looked for on
the three least significant bits (b3, b2, b1) of the 7-
bit Device Select Code. These inputs must be tied
to V CC or V SS , to establish the Device Select
Code.
Write Control (WC). This input signal is useful
for protecting the entire contents of the memory
from inadvertent write operations. Write opera-
tions are disabl ed to the entire memory array when
Write Control (WC) is driven High. When uncon-
nected, the signal is internally read as V IL , and
Write operations are allow ed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
Figure 4. Maximum R L Value versus Bus Capacitance (C BUS ) for an I 2 C Bus
20
V CC
16
R L
R L
12
SDA
8
MASTER
C BUS
SCL
fc = 100kHz
4
fc = 400kHz
C BUS
0
10
100
1000
C BUS (pF)
AI01665
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