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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
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Compal Confidential
2
2
ICW50 Schematics Document
AMD Turion/Sempron + Nvidia MCP67-MV
2007 / 04 / 20
Rev:1.0
FOR Pre-MP
3
3
4
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
2006/08/18
2006/08/18
2006/08/18
2007/8/18
2007/8/18
2007/8/18
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Cover Sheet
Cover Sheet
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
1.0
1.0
1.0
ICW50 / ICY70 LA-3581P
ICW50 / ICY70 LA-3581P
ICW50 / ICY70 LA-3581P
Date:
Date:
Date:
Friday, April 20, 2007
Friday, April 20, 2007
Friday, April 20, 2007
Sheet
Sheet
Sheet
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1
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of
of
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B
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Compal confidential
533/667/800
Project Code: ICW50
DDRII
DDRII-SO-DIMM X2
AMD Turion/Sempron CPU
Thermal Sensor
ADM1032ARM
File Name : LA-3581P
page 08,09
Socket S1 638P
page 4,5,6,7
Dual Channel
page 6
HT LINK
200-800MHz
D
D
DVI-D Conn.
LCD Conn.
CRT & TV-out
page 19
page 20
page 20
Nvidia
USB conn x4
Bluetooth
Conn
CMOS
Camera
MCP67-MV
LVDS
page 25,26
page 29
page 20
DVI
LVDS
836 BGA
USB 2.0 BUS
HD Audio
3.3V 24.576MHz/48Mhz
PCI-Express
IDE BUS
3.3V ATA-100
MXM II VGA/B
SATA BUS
CDROM
Conn.
MDC 1.5
Conn
HDA Codec
page 18
ALC268
page 21
page 29
page 31
C
PCI-Express
C
port 1
PCI BUS
3.3V 33 MHz
S-ATA HDD
Conn.
page 21
New Card
Socket
MINI Card x2
WLAN, TV-Tuner
PHY(GbE)
RTL8211B
page 22
IDSEL:AD20
(PIRQE#,
GNT#0,
REQ#0)
Audio AMP
page 10,11,12,13,14,15,16,17
page 32
Card Reader
Phone Jack x3
RICOH R5C833
page 23
LPC BUS
page 32
RJ45
page 22
1394
Conn.
6 in 1
socket
page 24
B
ENE KB926
B
page 23
page 27,28
Power On/Off CKT / LID switch / Power OK CKT
page 30
Int.KBD
Touch Pad
page 29
page 29
DC/DC Interface CKT.
CIR/LED
page 29
RTC CKT.
page 16
page 33
EC I/O Buffer
BIOS
page 29
page 29
Power Circuit DC/DC
page 35~41
CIR
page 30
A
A
Compal Secret Data
Compal Secret Data
Compal Secret Data
Security Classification
Security Classification
Security Classification
2006/08/18
2006/08/18
2006/08/18
2007/8/18
2007/8/18
2007/8/18
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
ICW50 / ICY70 LA-3581P
ICW50 / ICY70 LA-3581P
ICW50 / ICY70 LA-3581P
1.0
1.0
1.0
Date:
Date:
Date:
Friday, April 20, 2007
Friday, April 20, 2007
Friday, April 20, 2007
Sheet
Sheet
Sheet
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SIGNAL
STATE
SLP_S1# SLP_S3# SLP_S5# +VALW
+V
+VS
Clock
Voltage Rails
Full ON
HIGH
HIGH
HIGH
ON
ON
ON
ON
S1(Power On Suspend)
LOW
HIGH
HIGH
ON
ON
ON
LOW
Power Plane
Description
S1
S3
S5
VIN
B+
N/A
N/A
N/A
N/A
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
S3 (Suspend to RAM)
LOW
LOW
HIGH
ON
ON
OFF
OFF
D
N/A
N/A
D
S4 (Suspend to Disk)
LOW
LOW
HIGH
ON
OFF
OFF
OFF
ON
+CPU_CORE
OFF
OFF
+0.9V
0.9V switched power rail for DDR terminator
ON
ON
OFF
S5 (Soft OFF)
LOW
LOW
LOW
ON
OFF
OFF
OFF
+1.5VS
ON
1.5V switched power rail
OFF
OFF
+1.2VALW
1.2V always on power rail
ON
ON
ON*
Board ID / SKU ID Table for AD channel
+1.2VS
ON
1.2V switched power rail
OFF
OFF
+1.2V_HT
1.2V switched power rail
ON
OFF
OFF
Vcc
3.3V +/- 5%
100K +/- 5%
+1.8V
ON
ON
Ra/Rc/Re
Board ID
1.8V power rail for DDR
OFF
+1.8VS
1.8V switched power rail
ON
OFF
OFF
Rb / Rd / Rf
V
min
V
typ
V
AD_BID
max
AD_BID
AD_BID
+2.5VS
ON
0
1
2
3
0
8.2K +/- 5%
0 V
0.216 V
0 V
0 V
2.5V switched power rail
OFF
OFF
+3VALW/+3V/+3VAUX
3.3V always on power rail
ON
ON
ON*
0.250 V
0.289 V
+3VS
ON
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
0.436 V
0.712 V
0.503 V
0.819 V
0.538 V
0.875 V
3.3V switched power rail
5V always on power rail
OFF
OFF
ON*
+5VALW
ON
ON
+5VS
ON
4
5
6
7
1.036 V
1.453 V
1.185 V
1.264 V
5V switched power rail
OFF
OFF
+VSB
VSB always on power rail
ON
ON
ON*
1.650 V
1.759 V
ON
ON
ON
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
C
+RTCVCC
RTC power
C
NC
3.300 V
BOARD ID Table
BTO Option Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices
Device
Board ID
0
1
2
3
4
5
6
7
PCB Revision
BTO Item
BOM Structure
45@
UMA (0V)
DISCRETE (3.3V)
DIP CAP & RTC
UMA
IDSEL#
REQ#/GNT#
Interrupts
UMA@
AD20
0
1394
PIRQE
VGA
VGA@
UMA & TV-OUT
UMA&TV@
2 SATA HDD
SATA2@
CAMERA
CMOS@
BLUETOOTH
BT@
MINI CARD 1(TV)
MINI1@
MINI CARD 2(WLAN)
MINI2@
B
B
NEW CARD
EXPRESS@
EC SM Bus1 address
EC SM Bus2 address
SKU ID Table
TV-OUT
TV@
DVI
DVI@
SKU ID
0
1
2
3
4
5
6
7
SKU
Device
Address
Device
Address
1394
1394@
Smart Battery
ADM1032
B - PHASE
0001 011X b
1001 100X b
CARD READER
5IN1@
C - PHASE
HT Debug Port
HT@
MCP67 SM Bus address
Device
Address
DDR DIMM0
1001 000Xb
DDR DIMM2
1001 001Xb
A
A
Compal Secret Data
Compal Secret Data
Compal Secret Data
Security Classification
Security Classification
Security Classification
2006/08/18
2006/08/18
2006/08/18
2007/8/18
2007/8/18
2007/8/18
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
TABLE OF CONTENTS
TABLE OF CONTENTS
TABLE OF CONTENTS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
ICW50 / ICY70 LA-3581P
ICW50 / ICY70 LA-3581P
ICW50 / ICY70 LA-3581P
1.0
1.0
1.0
Date:
Date:
Date:
Friday, April 20, 2007
Friday, April 20, 2007
Friday, April 20, 2007
Sheet
Sheet
Sheet
3
3
3
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PROCESSOR HYPERTRANSPORT INTERFACE
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
D
D
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
FAN Conn
+1.2V_HT
JP22A
JP22A
VLDT_A3
C533
4.7U_0805_10V4Z
D4
AE5
1
2
VLDT_B3
D3
AE4
VLDT_A2
VLDT_B2
D2
AE3
VLDT_A1
VLDT_B1
+5VS
D1
AE2
VLDT_A0
VLDT_B0
H_CADIP15
H_CADOP15
N5
T4
D20
1SS355_SOD323-2
(10)
H_CADIP15
L0_CADIN_H15
L0_CADOUT_H15
H_CADOP15
(10)
H_CADIN15
H_CADON15
P5
T3
(10)
H_CADIN15
L0_CADIN_L15
L0_CADOUT_L15
H_CADON15
(10)
H_CADIP14
H_CADOP14
W=40mils
M3
V5
(10)
H_CADIP14
H_CADOP14
(10)
L0_CADIN_H14
L0_CADOUT_H14
H_CADIN14
H_CADON14
M4
U5
(10)
H_CADIN14
L0_CADIN_L14
L0_CADOUT_L14
H_CADON14
(10)
+VCC_FAN1
H_CADIP13
L5
V4
H_CADOP13
(10)
H_CADIP13
L0_CADIN_H13
L0_CADOUT_H13
H_CADOP13
(10)
H_CADIN13
H_CADON13
M5
V3
(10)
H_CADIN13
L0_CADIN_L13
L0_CADOUT_L13
H_CADON13
(10)
H_CADIP12
H_CADOP12
FAN1
K3
Y5
1
2
(10)
H_CADIP12
H_CADOP12
(10)
L0_CADIN_H12
L0_CADOUT_H12
+3VS
H_CADIN12
K4
W5
H_CADON12
C510
C510
10U_0805_10V4Z
10U_0805_10V4Z
(10)
H_CADIN12
L0_CADIN_L12
L0_CADOUT_L12
H_CADON12
(10)
H_CADIP11
H3
AB5
H_CADOP11
D21
BAS16_SOT23-3
(10)
H_CADIP11
L0_CADIN_H11
L0_CADOUT_H11
H_CADOP11
(10)
H_CADIN11
H_CADON11
H4
AA5
(10)
H_CADIN11
L0_CADIN_L11
L0_CADOUT_L11
H_CADON11
(10)
H_CADIP10
H_CADOP10
G5
AB4
1
2
(10)
H_CADIP10
H_CADOP10
(10)
L0_CADIN_H10
L0_CADOUT_H10
H_CADIN10
H5
AB3
H_CADON10
R88
10K_0402_5%
C509
C509
1000P_0402_50V7K
1000P_0402_50V7K
(10)
H_CADIN10
L0_CADIN_L10
L0_CADOUT_L10
H_CADON10
(10)
H_CADIP9
H_CADOP9
F3
AD5
Update Footprint
(10)
H_CADIP9
L0_CADIN_H9
L0_CADOUT_H9
H_CADOP9
(10)
H_CADIN9
H_CADON9
JP16
JP16
F4
AC5
(10)
H_CADIN9
L0_CADIN_L9
L0_CADOUT_L9
H_CADON9
(10)
H_CADIP8
H_CADOP8
E5
AD4
(10)
H_CADIP8
H_CADOP8
(10)
L0_CADIN_H8
L0_CADOUT_H8
1
2
3
H_CADIN8
H_CADON8
F5
AD3
(10)
H_CADIN8
L0_CADIN_L8
L0_CADOUT_L8
H_CADON8
(10)
(27,28)
FAN_SPEED1
C
H_CADIP7
N3
T1
H_CADOP7
C
(10)
H_CADIP7
L0_CADIN_H7
L0_CADOUT_H7
H_CADOP7
(10)
H_CADIN7
H_CADON7
N2
R1
(10)
H_CADIN7
L0_CADIN_L7
L0_CADOUT_L7
H_CADON7
(10)
H_CADIP6
H_CADOP6
ACES_85205-03001
ACES_85205-03001
L1
U2
1
(10)
H_CADIP6
H_CADOP6
(10)
L0_CADIN_H6
L0_CADOUT_H6
H_CADIN6
H_CADON6
M1
U3
(10)
H_CADIN6
H_CADON6
(10)
L0_CADIN_L6
L0_CADOUT_L6
H_CADIP5
L3
V1
H_CADOP5
C52
1000P_0402_50V7K
(10)
H_CADIP5
L0_CADIN_H5
L0_CADOUT_H5
H_CADOP5
(10)
H_CADIN5
H_CADON5
L2
U1
(10)
H_CADIN5
L0_CADIN_L5
L0_CADOUT_L5
H_CADON5
(10)
2
H_CADIP4
H_CADOP4
J1
W2
(10)
H_CADIP4
H_CADOP4
(10)
L0_CADIN_H4
L0_CADOUT_H4
H_CADIN4
H_CADON4
K1
W3
(10)
H_CADIN4
H_CADON4
(10)
L0_CADIN_L4
L0_CADOUT_L4
H_CADIP3
G1
AA2
H_CADOP3
(10)
H_CADIP3
L0_CADIN_H3
L0_CADOUT_H3
H_CADOP3
(10)
H_CADIN3
H_CADON3
H1
AA3
(10)
H_CADIN3
L0_CADIN_L3
L0_CADOUT_L3
H_CADON3
(10)
H_CADIP2
H_CADOP2
G3
AB1
(10)
H_CADIP2
H_CADOP2
(10)
L0_CADIN_H2
L0_CADOUT_H2
H_CADIN2
H_CADON2
G2
AA1
(10)
H_CADIN2
L0_CADIN_L2
L0_CADOUT_L2
H_CADON2
(10)
H_CADIP1
E1
AC2
H_CADOP1
(10)
H_CADIP1
L0_CADIN_H1
L0_CADOUT_H1
H_CADOP1
(10)
H_CADIN1
H_CADON1
U11
U11
F1
AC3
(10)
H_CADIN1
L0_CADIN_L1
L0_CADOUT_L1
H_CADON1
(10)
H_CADIP0
H_CADOP0
E3
AD1
1
8
(10)
H_CADIP0
H_CADOP0
(10)
L0_CADIN_H0
L0_CADOUT_H0
VEN
GND
H_CADIN0
H_CADON0
E2
AC1
2
7
(10)
H_CADIN0
H_CADON0
(10)
+5VS
+VCC_FAN1
L0_CADIN_L0
L0_CADOUT_L0
VIN
GND
3
6
VO
GND
H_CLKIP1
H_CLKOP1
H_CLKON1
EN_DFAN1
J5
Y4
4
5
(10)
H_CLKIP1
L0_CLKIN_H1
L0_CLKOUT_H1
H_CLKOP1
(10)
(27,28)
EN_DFAN1
VSET
GND
H_CLKIN1
H_CLKIN0
K5
Y3
1
(10)
H_CLKIN1
H_CLKON1
(10)
L0_CLKIN_L1
L0_CLKOUT_L1
H_CLKIP0
H_CLKOP0
G993P1UF_SOP8
G993P1UF_SOP8
J3
Y1
(10)
H_CLKIP0
H_CLKOP0
(10)
L0_CLKIN_H0
L0_CLKOUT_H0
+1.2V_HT
J2
W1
H_CLKON0
C310
10U_0805_10V4Z
(10)
H_CLKIN0
L0_CLKIN_L0
L0_CLKOUT_L0
H_CLKON0
(10)
2
R143
R143
51_0402_1%
51_0402_1%
H_CTLIP1
1
2
P3
T5
L0_CTLIN_H1
L0_CTLOUT_H1
R142
R142
1
2
51_0402_1%
51_0402_1%
H_CTLIN1
P4
R5
L0_CTLIN_L1
L0_CTLOUT_L1
H_CTLIP0
H_CTLOP0
FAN1 Conn
N1
R2
(10)
H_CTLIP0
L0_CTLIN_H0
L0_CTLOUT_H0
H_CTLOP0
(10)
H_CTLIN0
H_CTLON0
P1
R3
(10)
H_CTLIN0
H_CTLON0
(10)
L0_CTLIN_L0
L0_CTLOUT_L0
FOX_PZ63823-284S-41F
FOX_PZ63823-284S-41F
B
Athlon 64 S1
Processor Socket
B
+1.2V_HT
C541
4.7U_0805_10V4Z
C536
0.22U_0402_10V4Z
C539
180P_0402_50V8J
1
1
1
1
1
1
2
2
2
2
2
2
C542
4.7U_0805_10V4Z
C540
0.22U_0402_10V4Z
C538
180P_0402_50V8J
LAYOUT: Place bypass cap on topside of board
NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
TO OTHER HT POWER PINS
PLACE CLOSE TO VLDT0 POWER PINS
A
A
Compal Secret Data
Compal Secret Data
Compal Secret Data
Security Classification
Security Classification
Security Classification
2006/08/18
2006/08/18
2006/08/18
2007/8/18
2007/8/18
2007/8/18
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
AMD CPU HT I/F
AMD CPU HT I/F
AMD CPU HT I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
ICW50 / ICY70 LA-3581P
ICW50 / ICY70 LA-3581P
ICW50 / ICY70 LA-3581P
1.0
1.0
1.0
Date:
Date:
Date:
Friday, April 20, 2007
Friday, April 20, 2007
Friday, April 20, 2007
Sheet
Sheet
Sheet
4
4
4
of
of
of
42
42
42
5
4
3
2
1
A
B
C
D
E
Processor DDR2 Memory Interface
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
JP22C
JP22C
(9)
DDR_B_D[63..0]
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
DDR_A_D[63..0]
(8)
DDR_B_D63
DDR_A_D63
AD11
AA12
MB_DATA63
MA_DATA63
DDR_B_D62
AF11
AB12
DDR_A_D62
DDR_A_D61
MB_DATA62
MA_DATA62
DDR_B_D61
AF14
AA14
MB_DATA61
MA_DATA61
DDR_B_D60
DDR_A_D60
AE14
AB14
MB_DATA60
MA_DATA60
DDR_B_D59
DDR_A_D59
Y11
W11
MB_DATA59
MA_DATA59
DDR_B_D58
DDR_A_D58
DDR_A_D56
AB11
Y12
MB_DATA58
MA_DATA58
DDR_B_D57
DDR_A_D57
DDR_A_D55
AC12
AD13
MB_DATA57
MA_DATA57
+1.8V
DDR_B_D56
AF13
AB13
MB_DATA56
MA_DATA56
DDR_B_D55
+0.9VREF_CPU
AF15
AD15
MB_DATA55
MA_DATA55
4
JP22B
JP22B
+0.9V
DDR_B_D54
DDR_A_D54
4
AF16
AB15
MB_DATA54
MA_DATA54
DDR_B_D53
DDR_A_D53
AC18
AB17
MB_DATA53
MA_DATA53
DDR_B_D52
DDR_A_D52
W17
D10
AF19
Y17
M_VREF
VTT1
MB_DATA52
MA_DATA52
R386
39.2_0402_1%~D
C10
DDR_B_D51
AD14
Y14
DDR_A_D51
VTT2
MB_DATA51
MA_DATA51
PAD
PAD
TP2
TP2
VTT_SENSE
Y10
B10
DDR_B_D50
AC14
W14
DDR_A_D50
VTT_SENSE
VTT3
MB_DATA50
MA_DATA50
DDR_B_D49
DDR_A_D49
AD10
AE18
W16
VTT4
MB_DATA49
MA_DATA49
DDR_B_D48
DDR_A_D48
W10
AD18
AD17
VTT5
MB_DATA48
MA_DATA48
M_ZN
DDR_B_D47
DDR_A_D47
AE10
AC10
AD20
Y18
M_ZN
VTT6
MB_DATA47
MA_DATA47
M_ZP
DDR_B_D46
DDR_A_D46
AF10
AB10
AC20
AD19
M_ZP
VTT7
MB_DATA46
MA_DATA46
10:8:10:8:10
AA10
DDR_B_D45
AF23
AD21
DDR_A_D45
VTT8
MB_DATA45
MA_DATA45
R388
39.2_0402_1%~D
DDR_B_D44
DDR_A_D44
A10
AF24
AB21
VTT9
MB_DATA44
MA_DATA44
DDR_B_D43
DDR_A_D43
AF20
AB18
MB_DATA43
MA_DATA43
DDR_CS3_DIMMA#
DDR_A_CLK2
DDR_B_D42
DDR_A_D42
V19
Y16
AE20
AA18
(8)
DDR_CS3_DIMMA#
MA0_CS_L3
MA0_CLK_H2
DDR_A_CLK2 (8)
DDR_A_CLK#2 (8)
DDR_A_CLK1 (8)
DDR_A_CLK#1 (8)
DDR_B_CLK2 (9)
DDR_B_CLK#2 (9)
DDR_B_CLK1 (9)
DDR_B_CLK#1 (9)
DDR_B_ODT1 (9)
DDR_B_ODT0 (9)
DDR_A_ODT1 (8)
DDR_A_ODT0 (8)
DDR_B_MA[15..0]
MB_DATA42
MA_DATA42
DDR_CS2_DIMMA#
DDR_A_CLK#2
DDR_B_D41
DDR_A_D41
J22
AA16
AD22
AA20
(8)
DDR_CS2_DIMMA#
MA0_CS_L2
MA0_CLK_L2
MB_DATA41
MA_DATA41
DDR_CS1_DIMMA#
V22
E16
DDR_A_CLK1
DDR_B_D40
AC22
Y20
DDR_A_D40
(8)
DDR_CS1_DIMMA#
MA0_CS_L1
MA0_CLK_H1
MB_DATA40
MA_DATA40
DDR_CS0_DIMMA#
T19
F16
DDR_A_CLK#1
DDR_B_D39
AE25
AA22
DDR_A_D39
(8)
DDR_CS0_DIMMA#
MA0_CS_L0
MA0_CLK_L1
MB_DATA39
MA_DATA39
DDR_B_D38
DDR_A_D38
AD26
Y22
MB_DATA38
MA_DATA38
DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_B_CLK2
DDR_B_D37
DDR_A_D37
Y26
AF18
AA25
W21
(9)
DDR_CS3_DIMMB#
MB0_CS_L3
MB0_CLK_H2
MB_DATA37
MA_DATA37
DDR_B_CLK#2
DDR_B_D36
DDR_A_D36
J24
AF17
AA26
W22
(9)
DDR_CS2_DIMMB#
MB0_CS_L2
MB0_CLK_L2
MB_DATA36
MA_DATA36
DDR_CS1_DIMMB#
W24
A17
DDR_B_CLK1
DDR_B_D35
AE24
AA21
DDR_A_D35
(9)
DDR_CS1_DIMMB#
MB0_CS_L1
MB0_CLK_H1
MB_DATA35
MA_DATA35
PLACE THEM CLOSE TO
CPU WITHIN 1"
DDR_CS0_DIMMB#
U23
A18
DDR_B_CLK#1
DDR_B_D34
AD24
AB22
DDR_A_D34
(9)
DDR_CS0_DIMMB#
MB0_CS_L0
MB0_CLK_L1
MB_DATA34
MA_DATA34
DDR_B_D33
DDR_A_D33
AA23
AB24
MB_DATA33
MA_DATA33
DDR_CKE1_DIMMB
DDR_B_ODT1
DDR_B_D32
DDR_A_D32
H26
W23
AA24
Y24
(9)
DDR_CKE1_DIMMB
MB_CKE1
MB0_ODT1
MB_DATA32
MA_DATA32
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_B_ODT0
DDR_B_D31
DDR_A_D31
J23
W26
G24
H22
(9)
DDR_CKE0_DIMMB
MB_CKE0
MB0_ODT0
MB_DATA31
MA_DATA31
DDR_A_ODT1
DDR_B_D30
DDR_A_D30
J20
V20
G23
H20
(8)
DDR_CKE1_DIMMA
MA_CKE1
MA0_ODT1
MB_DATA30
MA_DATA30
DDR_CKE0_DIMMA
J21
U19
DDR_A_ODT0
DDR_B_D29
D26
E22
DDR_A_D29
(8)
DDR_A_MA[15..0]
DDR_CKE0_DIMMA
MA_CKE0
MA0_ODT0
MB_DATA29
MA_DATA29
DDR_B_D28
C26
E21
DDR_A_D28
DDR_A_D26
(8)
(9)
MB_DATA28
MA_DATA28
DDR_A_MA15
DDR_B_MA15
DDR_B_D27
DDR_A_D27
K19
J25
G26
J19
MA_ADD15
MB_ADD15
MB_DATA27
MA_DATA27
DDR_A_MA14
DDR_B_MA14
DDR_B_D26
K20
J26
G25
H24
MA_ADD14
MB_ADD14
MB_DATA26
MA_DATA26
DDR_A_MA13
DDR_B_MA13
DDR_B_MA11
DDR_B_D25
DDR_A_D25
V24
W25
E24
F22
MA_ADD13
MB_ADD13
MB_DATA25
MA_DATA25
DDR_A_MA12
K24
L23
DDR_B_MA12
DDR_B_D24
E23
F20
DDR_A_D24
MA_ADD12
MB_ADD12
MB_DATA24
MA_DATA24
DDR_A_MA11
L20
L25
DDR_B_D23
C24
C23
DDR_A_D23
MA_ADD11
MB_ADD11
MB_DATA23
MA_DATA23
DDR_A_MA10
DDR_B_MA10
DDR_B_D22
DDR_A_D22
R19
U25
B24
B22
MA_ADD10
MB_ADD10
MB_DATA22
MA_DATA22
DDR_A_MA9
DDR_B_MA9
DDR_B_D21
DDR_A_D21
L19
L24
C20
F18
MA_ADD9
MB_ADD9
MB_DATA21
MA_DATA21
DDR_A_MA8
DDR_B_MA8
DDR_B_D20
DDR_A_D20
L22
M26
B20
E18
MA_ADD8
MB_ADD8
MB_DATA20
MA_DATA20
DDR_A_MA7
DDR_B_MA7
DDR_B_D19
DDR_A_D19
L21
L26
C25
E20
MA_ADD7
MB_ADD7
MB_DATA19
MA_DATA19
DDR_A_MA6
M19
N23
DDR_B_MA6
DDR_B_D18
D24
D22
DDR_A_D18
MA_ADD6
MB_ADD6
MB_DATA18
MA_DATA18
DDR_A_MA5
DDR_B_MA5
DDR_B_D17
DDR_A_D17
M20
N24
A21
C19
MA_ADD5
MB_ADD5
MB_DATA17
MA_DATA17
3
DDR_A_MA4
DDR_B_MA4
DDR_B_D16
DDR_A_D16
3
M24
N25
D20
G18
MA_ADD4
MB_ADD4
MB_DATA16
MA_DATA16
DDR_A_MA3
DDR_A_MA1
DDR_B_MA3
DDR_B_D15
DDR_A_D15
M22
N26
D18
G17
MA_ADD3
MB_ADD3
MB_DATA15
MA_DATA15
DDR_A_MA2
DDR_B_MA2
DDR_B_D14
DDR_A_D14
N22
P24
C18
C17
MA_ADD2
MB_ADD2
MB_DATA14
MA_DATA14
N21
P26
DDR_B_MA1
DDR_B_D13
D14
F14
DDR_A_D13
MA_ADD1
MB_ADD1
MB_DATA13
MA_DATA13
DDR_A_MA0
R21
T24
DDR_B_MA0
DDR_B_D12
C14
E14
DDR_A_D12
MA_ADD0
MB_ADD0
MB_DATA12
MA_DATA12
DDR_B_D11
DDR_A_D11
A20
H17
MB_DATA11
MA_DATA11
DDR_A_BS#2
DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0
DDR_B_D10
DDR_A_D10
K22
K26
A19
E17
(8)
DDR_A_BS#2
MA_BANK2
MB_BANK2
DDR_B_BS#2
(9)
MB_DATA10
MA_DATA10
DDR_A_BS#1
DDR_B_D9
DDR_A_D9
R20
T26
A16
E15
(8)
DDR_A_BS#1
MA_BANK1
MB_BANK1
DDR_B_BS#1
(9)
MB_DATA9
MA_DATA9
DDR_A_BS#0
DDR_B_D8
DDR_B_D7
DDR_A_D8
T22
U26
A15
H15
(8)
DDR_A_BS#0
MA_BANK0
MB_BANK0
DDR_B_BS#0
(9)
MB_DATA8
MA_DATA8
A13
E13
DDR_A_D7
MB_DATA7
MA_DATA7
DDR_A_RAS#
DDR_B_RAS#
DDR_B_D6
DDR_A_D6
T20
U24
D12
C13
(8)
DDR_A_RAS#
DDR_B_RAS#
(9)
MA_RAS_L
MB_RAS_L
MB_DATA6
MA_DATA6
DDR_A_CAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_D5
DDR_A_D5
U20
V26
E11
H12
(8)
DDR_A_CAS#
DDR_B_CAS#
(9)
MA_CAS_L
MB_CAS_L
MB_DATA5
MA_DATA5
DDR_A_WE#
DDR_B_D4
DDR_A_D4
U21
U22
G11
H11
(8)
DDR_A_WE#
MA_WE_L
MB_WE_L
DDR_B_WE#
(9)
MB_DATA4
MA_DATA4
DDR_B_D3
DDR_A_D3
B14
G14
MB_DATA3
MA_DATA3
FOX_PZ63823-284S-41F
FOX_PZ63823-284S-41F
DDR_B_D2
A14
H14
DDR_A_D2
MB_DATA2
MA_DATA2
Athlon 64 S1
Processor
Socket
DDR_B_D1
A11
F12
DDR_A_D1
MB_DATA1
MA_DATA1
DDR_B_D0
DDR_A_D0
C11
G12
MB_DATA0
MA_DATA0
(9)
DDR_B_DM[7..0]
DDR_A_DM[7..0]
(8)
DDR_B_DM7
DDR_A_DM7
AD12
Y13
MB_DM7
MA_DM7
DDR_B_DM6
AC16
AB16
DDR_A_DM6
MB_DM6
MA_DM6
DDR_B_DM5
AE22
Y19
DDR_A_DM5
MB_DM5
MA_DM5
DDR_B_DM4
DDR_A_DM4
AB26
AC24
MB_DM4
MA_DM4
DDR_A_CLK2
DDR_B_CLK2
DDR_B_DM3
DDR_A_DM3
E25
F24
MB_DM3
MA_DM3
DDR_B_DM2
DDR_A_DM2
1
1
A22
E19
MB_DM2
MA_DM2
DDR_B_DM1
DDR_A_DM1
B16
C15
MB_DM1
MA_DM1
C336
1.5P_0402_50V8C
C349
1.5P_0402_50V8C
DDR_B_DM0
A12
E12
DDR_A_DM0
MB_DM0
MA_DM0
2
2
DDR_A_CLK#2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_DQS7
DDR_B_DQS#7
DDR_A_DQS7
DDR_A_DQS#7
AF12
W12
(9)
DDR_B_DQS7
DDR_A_DQS7
(8)
MB_DQS_H7
MA_DQS_H7
AE12
W13
(9)
DDR_B_DQS#7
MB_DQS_L7
MA_DQS_L7
DDR_A_DQS#7
(8)
DDR_A_CLK1
DDR_B_DQS6
DDR_B_DQS#6
DDR_A_DQS6
DDR_A_DQS#6
AE16
Y15
(9)
DDR_B_DQS6
MB_DQS_H6
MA_DQS_H6
DDR_A_DQS6
(8)
AD16
W15
1
1
(9)
DDR_B_DQS#6
MB_DQS_L6
MA_DQS_L6
DDR_A_DQS#6
(8)
DDR_B_DQS5
DDR_B_DQS#5
AF21
AB19
DDR_A_DQS5
DDR_A_DQS#5
(9)
DDR_B_DQS5
MB_DQS_H5
MA_DQS_H5
DDR_A_DQS5
(8)
C344
1.5P_0402_50V8C
C348
1.5P_0402_50V8C
AF22
AB20
(9)
DDR_B_DQS#5
DDR_A_DQS#5
(8)
MB_DQS_L5
MA_DQS_L5
DDR_B_DQS4
DDR_B_DQS#4
DDR_A_DQS4
DDR_A_DQS#4
AC25
AD23
(9)
DDR_B_DQS4
DDR_A_DQS4
(8)
2
2
MB_DQS_H4
MA_DQS_H4
DDR_A_CLK#1
DDR_B_CLK#1
AC26
AC23
(9)
DDR_B_DQS#4
MB_DQS_L4
MA_DQS_L4
DDR_A_DQS#4
(8)
DDR_B_DQS3
DDR_B_DQS#3
DDR_A_DQS3
DDR_A_DQS#3
F26
G22
(9)
DDR_B_DQS3
MB_DQS_H3
MA_DQS_H3
DDR_A_DQS3
(8)
E26
G21
(9)
DDR_B_DQS#3
MB_DQS_L3
MA_DQS_L3
DDR_A_DQS#3
(8)
DDR_B_DQS2
DDR_B_DQS#2
DDR_A_DQS2
DDR_A_DQS#2
PLACE CLOSE TO PROCESSOR
WITHIN 1.2 INCH
PLACE CLOSE TO PROCESSOR
WITHIN 1.2 INCH
A24
C22
(9)
DDR_B_DQS2
DDR_A_DQS2
(8)
MB_DQS_H2
MA_DQS_H2
2
2
A23
C21
(9)
DDR_B_DQS#2
DDR_A_DQS#2
(8)
MB_DQS_L2
MA_DQS_L2
DDR_B_DQS1
DDR_B_DQS#1
DDR_A_DQS1
DDR_A_DQS#1
D16
G16
(9)
DDR_B_DQS1
MB_DQS_H1
MA_DQS_H1
DDR_A_DQS1
(8)
C16
G15
(9)
DDR_B_DQS#1
MB_DQS_L1
MA_DQS_L1
DDR_A_DQS#1
(8)
DDR_B_DQS0
DDR_B_DQS#0
C12
G13
DDR_A_DQS0
DDR_A_DQS#0
(9)
DDR_B_DQS0
MB_DQS_H0
MA_DQS_H0
DDR_A_DQS0
(8)
B12
H13
(9)
DDR_B_DQS#0
MB_DQS_L0
MA_DQS_L0
DDR_A_DQS#0
(8)
FOX_PZ63823-284S-41F
FOX_PZ63823-284S-41F
Athlon 64 S1
Processor Socket
+1.8V
R228
1K_0402_1%
+0.9VREF_CPU
CPU_VREF_REF
A1
A26
1
1
1
1
1
C358
C358
C363
1000P_0402_50V7K
C345
0.1U_0402_16V4Z
C357
C357
C350
1U_0402_6.3V4Z
R222
1K_0402_1%
2
2
2
2
2
Athlon 64 S1g1
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
uPGA638
Top View
VDD_VREF_SUS_CPU
LAYOUT:PLACE CLOSE TO CPU
AF1
1
1
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
2006/08/18
2006/08/18
2006/08/18
2007/8/18
2007/8/18
2007/8/18
Issued Date
Issued Date
Issued Date
Title
Title
Title
Deciphered Date
Deciphered Date
Deciphered Date
AMD CPU DDRII MEMORY I/F
AMD CPU DDRII MEMORY I/F
AMD CPU DDRII MEMORY I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
ICW50 / ICY70 LA-3581P
ICW50 / ICY70 LA-3581P
ICW50 / ICY70 LA-3581P
1.0
1.0
1.0
Date:
Date:
Date:
Friday, April 20, 2007
Friday, April 20, 2007
Friday, April 20, 2007
Sheet
Sheet
Sheet
5
5
5
of
of
of
42
42
42
A
B
C
D
E
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mfireb
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2107445118.pdf
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2890101021.pdf
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895485620.pdf
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