intel-io-controller-hub-8-datasheet.pdf

Intel ® I/O Controller Hub 8 (ICH8)

Family

Datasheet

– For the Intel ® 82801HB ICH8, 82801HR ICH8R, 82801HDH ICH8DH,

82801HDO ICH8DO, 82801HBM ICH8M, and 82801HEM ICH8M-E

I/O Controller Hubs

May 2007

Document Number: 313056-003

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future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel ® I/O Controller Hub 8 (ICH8) Family chipset component may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

I 2 C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I 2 C bus/protocol and was developed by Intel.

Implementations of the I 2 C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips

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Intel ® ICH8 Family Datasheet

Contents

Introduction ............................................................................................................ 45

1.1

Overview ......................................................................................................... 48

Intel ® ICH8 Family High-Level Component Differences ........................................... 55

1.2

Signal Description ................................................................................................... 57

2.1

Direct Media Interface (DMI) to Host Controller ..................................................... 60

2.2

PCI Express* .................................................................................................... 60

2.3

LAN Connect Interface ....................................................................................... 61

2.4

Gigabit LAN Connect Interface ............................................................................ 61

2.5

Firmware Hub Interface...................................................................................... 62

2.6

PCI Interface .................................................................................................... 63

2.7

Serial ATA Interface........................................................................................... 66

2.8

IDE Interface (Mobile Only) ................................................................................ 68

2.9

LPC Interface.................................................................................................... 69

2.10

Interrupt Interface ............................................................................................ 70

2.11

USB Interface ................................................................................................... 71

2.12

Power Management Interface.............................................................................. 72

2.13

Processor Interface............................................................................................ 75

2.14

SMBus Interface................................................................................................ 77

2.15

System Management Interface............................................................................ 77

2.16

Real Time Clock Interface ................................................................................... 78

2.17

Other Clocks..................................................................................................... 79

2.18

Miscellaneous Signals ........................................................................................ 79

Intel ® High Definition Audio Link ......................................................................... 80

2.19

2.20

Serial Peripheral Interface (SPI) .......................................................................... 81

Intel ® Quick Resume Technology (Intel ® ICH8DH Only) ......................................... 82

2.21

2.22

Controller Link .................................................................................................. 82

Intel ® Quiet System Technology (Desktop Only) ................................................... 83

2.23

2.24

General Purpose I/O Signals ............................................................................... 83

2.25

Power and Ground............................................................................................. 86

2.26

Pin Straps ........................................................................................................ 88

2.26.1 Functional Straps ................................................................................... 88

2.26.2 External RTC Circuitry............................................................................. 90

Intel ® ICH8 Pin States ............................................................................................. 91

3.1

Integrated Pull-Ups and Pull-Downs ..................................................................... 91

3.2

IDE Integrated Series Termination Resistors (Mobile Only)...................................... 92

3.3

Output and I/O Signals Planes and States............................................................. 92

3.4

Power Planes for Input Signals .......................................................................... 102

Intel ® ICH8 and System Clock Domains ................................................................. 107

Functional Description ........................................................................................... 109

5.1

PCI-to-PCI Bridge (D30:F0) .............................................................................. 109

5.1.1

PCI Bus Interface ................................................................................. 109

5.1.2

PCI Bridge As an Initiator ...................................................................... 109

5.1.2.1

Memory Reads and Writes........................................................ 110

5.1.2.2

Configuration Reads and Writes ................................................ 110

5.1.2.3

Locked Cycles ........................................................................ 110

5.1.2.4

Target / Master Aborts............................................................. 110

5.1.2.5

Secondary Master Latency Timer............................................... 110

5.1.2.6

Dual Address Cycle (DAC) ........................................................ 110

5.1.2.7

Memory and I/O Decode to PCI................................................. 111

5.1.3

Parity Error Detection and Generation ..................................................... 111

Intel ® ICH8 Family Datasheet

5.1.4

PCIRST# ............................................................................................. 111

5.1.5

Peer Cycles .......................................................................................... 112

5.1.6

PCI-to-PCI Bridge Model ........................................................................ 112

5.1.7

IDSEL to Device Number Mapping ........................................................... 112

5.1.8

Standard PCI Bus Configuration Mechanism.............................................. 113

5.2

PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5) ................................................ 113

5.2.1

Interrupt Generation ............................................................................. 113

5.2.2

Power Management...............................................................................114

5.2.2.1

S3/S4/S5 Support ................................................................... 114

5.2.2.2

Resuming from Suspended State ............................................... 114

5.2.2.3

Device Initiated PM_PME Message ............................................. 114

5.2.2.4

SMI/SCI Generation................................................................. 115

5.2.3

SERR# Generation ................................................................................ 115

5.2.4

Hot-Plug .............................................................................................. 115

5.2.4.1

Presence Detection .................................................................. 115

5.2.4.2

Message Generation ................................................................ 116

5.2.4.3

Attention Button Detection ....................................................... 116

5.2.4.4

SMI/SCI Generation................................................................. 117

5.3

Gigabit Ethernet Controller (B0:D25:F0) ............................................................. 118

5.3.1

GbE PCI Bus Interface ........................................................................... 118

5.3.1.1

Transaction Layer.................................................................... 118

5.3.1.2

Data Alignment ....................................................................... 118

5.3.1.3

Configuration Request Retry Status ........................................... 119

5.3.2

Error Events and Error Reporting ............................................................ 119

5.3.2.1

Data Parity Error ..................................................................... 119

5.3.2.2

Completion with Unsuccessful Completion Status ......................... 119

5.3.3

Ethernet Interface ................................................................................ 119

5.3.3.1

MAC/LAN Connect Interface ...................................................... 119

5.3.4

PCI Power Management ......................................................................... 120

5.3.4.1

Wake-Up................................................................................ 120

5.3.5

Configurable LEDs................................................................................. 122

Intel ® Auto Connect Battery Saver (Mobile Only) ...................................... 122

5.3.6.1

5.3.6

Partial and Full Power Down Options .......................................... 123

Intel ® ACBS Signal Configurations ............................................. 123

5.3.6.2

5.4

LPC Bridge (w/ System and Management Functions) (D31:F0) ............................... 124

5.4.1

LPC Interface ....................................................................................... 124

5.4.1.1 LPC Cycle Types ...................................................................... 125

5.4.1.2 Start Field Definition ................................................................ 125

5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR)..................................... 126

5.4.1.4 Size....................................................................................... 126

5.4.1.5 SYNC..................................................................................... 127

5.4.1.6 SYNC Time-Out ....................................................................... 127

5.4.1.7 SYNC Error Indication .............................................................. 127

5.4.1.8 LFRAME# Usage...................................................................... 127

5.4.1.9 I/O Cycles .............................................................................. 128

5.4.1.10 Bus Master Cycles ................................................................... 128

5.4.1.11 LPC Power Management ........................................................... 128

5.4.1.12 Configuration and Intel ® ICH8 Implications................................. 128

5.5

DMA Operation (D31:F0) .................................................................................. 129

5.5.1

Channel Priority.................................................................................... 129

5.5.1.1

Fixed Priority .......................................................................... 130

5.5.1.2

Rotating Priority ...................................................................... 130

5.5.2

Address Compatibility Mode ................................................................... 130

5.5.3

Summary of DMA Transfer Sizes ............................................................. 131

5.5.3.1

Address Shifting When Programmed for 16-Bit I/O

Count by Words ...................................................................... 131

5.5.4

Autoinitialize ........................................................................................ 131

Intel ® ICH8 Family Datasheet

5.5.5

Software Commands............................................................................. 132

5.6

LPC DMA ........................................................................................................ 132

5.6.1

Asserting DMA Requests........................................................................ 132

5.6.2

Abandoning DMA Requests .................................................................... 133

5.6.3

General Flow of DMA Transfers............................................................... 133

5.6.4

Terminal Count .................................................................................... 133

5.6.5

Verify Mode ......................................................................................... 134

5.6.6

DMA Request Deassertion...................................................................... 134

5.6.7

SYNC Field / LDRQ# Rules..................................................................... 135

5.7

8254 Timers (D31:F0) ..................................................................................... 135

5.7.1

Timer Programming .............................................................................. 136

5.7.2

Reading from the Interval Timer............................................................. 137

5.7.2.1

Simple Read........................................................................... 137

5.7.2.2

Counter Latch Command.......................................................... 137

5.7.2.3

Read Back Command .............................................................. 138

5.8

8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 139

5.8.1

Interrupt Handling................................................................................ 140

5.8.1.1

Generating Interrupts.............................................................. 140

5.8.1.2

Acknowledging Interrupts ........................................................ 140

5.8.1.3

Hardware/Software Interrupt Sequence ..................................... 141

5.8.2

Initialization Command Words (ICWx)..................................................... 141

5.8.2.1

ICW1 .................................................................................... 141

5.8.2.2

ICW2 .................................................................................... 142

5.8.2.3

ICW3 .................................................................................... 142

5.8.2.4

ICW4 .................................................................................... 142

5.8.3

Operation Command Words (OCW)......................................................... 142

5.8.4

Modes of Operation .............................................................................. 143

5.8.4.1 Fully Nested Mode................................................................... 143

5.8.4.2 Special Fully-Nested Mode........................................................ 143

5.8.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 143

5.8.4.4 Specific Rotation Mode (Specific Priority).................................... 143

5.8.4.5 Poll Mode............................................................................... 144

5.8.4.6 Cascade Mode ........................................................................ 144

5.8.4.7 Edge and Level Triggered Mode ................................................ 144

5.8.4.8 End of Interrupt (EOI) Operations ............................................. 144

5.8.4.9 Normal End of Interrupt........................................................... 144

5.8.4.10 Automatic End of Interrupt Mode .............................................. 145

5.8.5

Masking Interrupts ............................................................................... 145

5.8.5.1

Masking on an Individual Interrupt Request ................................ 145

5.8.5.2

Special Mask Mode.................................................................. 145

5.8.6

Steering PCI Interrupts ......................................................................... 145

5.9

Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 146

5.9.1

Interrupt Handling................................................................................ 146

5.9.2

Interrupt Mapping ................................................................................ 146

5.9.3

PCI / PCI Express* Message-Based Interrupts .......................................... 147

5.9.4

Front Side Bus Interrupt Delivery ........................................................... 147

5.9.4.1

Edge-Triggered Operation ........................................................ 148

5.9.4.2

Level-Triggered Operation........................................................ 148

5.9.4.3

Registers Associated with Front Side Bus Interrupt Delivery.......... 148

5.9.4.4

Interrupt Message Format........................................................ 148

5.10

Serial Interrupt (D31:F0) ................................................................................. 149

5.10.1 Start Frame......................................................................................... 149

5.10.2 Data Frames........................................................................................ 150

5.10.3 Stop Frame ......................................................................................... 150

5.10.4 Specific Interrupts Not Supported via SERIRQ .......................................... 150

5.10.5 Data Frame Format .............................................................................. 151

Intel ® ICH8 Family Datasheet

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