volume39-number1(1).pdf
(
757 KB
)
Pobierz
A forum for the exchange of circuits, systems, and software for real-world signal processing
Volume 39, Number 1, 2005
In This Issue
Editors’ Notes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
A Smart Modem for Robust Wireless Data Transmission
Over ISM Bands (433 MHz, 868 MHz, and 902 MHz)
. . . . . . . . . . . . . . . . . . . . . . . . 3
Blackfin
®
Processor’s Parallel Peripheral Interface Simplifies LCD
Connection in Portable Multimedia
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Enhance Processor Performance in Open-Source Applications
. . . . . . . . . . . . . . . . . . 11
Authors
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
�����������������������������
Editors’ Notes
40 YEARS OF REAL WORLD SIGNAL PROCESSING
Forty years ago, Ray Stata and Matt Lorber
opened the doors of Analog Devices for
business, offering a line of high-performance
operational amplifiers. We’ve survived and
prospered beyond their fondest expectations,
and are still rarin’ to go. In celebration of
that anniversary,
Analog Dialogue’s
four print
installments will each be devoted to one of our
major technologies. We start with digital signal
processing (DSP).
ANALOG SIGNAL PROCESSING GOES DIGITAL
In 1986, a new—and apparently unlikely—contender entered the young
ield of digital-signal-processor manufacturing—then dominated by TI,
the colossus of “Speak & Spell,”—with a single-chip DSP, our ADSP-2100.
As we celebrate our 40
th
year in the business of components for signal
processing, it seems worthwhile to reproduce here our editorial comments
that accompanied the introduction of the irst Analog Devices DSP in these
pages (
Analog Dialogue
20-2, 1986):
“Microprocessor?” we hear you ask. “Isn’t it a bit unseemly for a nice
‘Analog’ IC company to be designing a microprocessor? (What could
be more
digital
?)”
Good question.
Our objective has always been to design and manufacture cost-effective
components that are key elements of the signal path for processing real-
world (i.e.,
analog
) data and for which performance is maximized and
errors minimized.
The signal path?
Real-world data
almost always starts out as
analog
(i.e., parallel, non-numeric) variables, which are measured by sensors
that provide
analog
electrical signals—voltage and current. The signals
must be accurately and speedily ampliied, conditioned (almost always in
parallel) and converted to digital for processing. Once in digital form, they
must be processed rapidly. Often they again wind up as analog signals.
Key elements of the signal path may include preampliiers, analog
signal processors, data converters—to and from digital—and, when
the signal is in digital form, a digital processor. Inadequacy in any one
of the key elements—ampliier, analog processor, data converter, or
microprocessor—can cause poor performance of the overall system.
Obstacles in the signal path include noise, drift, nonlinearity, and
measurement lag at the analog stages, similar obstacles in conversion—
and throughput delays in digital processing, often because of the lack of
parallelism in von Neumann architectures.
Throughout our history, ADI’s role in the signal path has been to initiate
new products (or product lines) when dissatisied with the performance
and cost-effectiveness of what’s available (which is often limited to user-
assembled kludges, when nothing else is available). At this point in time,
we (and our worthy competitors) have virtually eliminated the user-
assembled ampliier, signal conditioner, and data converter, by designing
and marketing families of high-performance, cost-effective products.
We have always been dissatisied with the cost, power dissipation, and
slow throughput in the digital domain; this concern led to our pioneering
development of CMOS multipliers and other digital signal-processing
ICs (note that because we were already familiar with analog multipliers,
digital multipliers became just another analog signal-processing tool).
Note also our commitment to
signal processing
—not payroll, desktop
publishing, or order-handling products).
And our dissatisfaction with insuficient throughput in DSP processors
led to the design of the ADSP-2100, which stresses the use of that
analog
characteristic, parallelism, to minimize instruction cycles, whether in
processing, data transfer, or interrupt handling. It’s neat! We invite you
to read about it.
Since that time, such names as SHARC
®
, TigerSHARC
®
, Blackfin
®
,
EZ Kit, and VisualDSP++
®
have become household words, as they
remove barriers whenever DSPs are considered.
Dan Sheingold
[
dan.sheingold@analog.com
]
FROM NUMBER CRUNCHING TO MULTIMEDIA
In the early days of digital signal processing,
the ADSP-2100 single-chip microprocessor
was typically used for applications that required
high-speed numeric processing. Integrating
a 16-bit arithmetic-logic unit (ALU), 16-bit
multiplier-accumulator (MAC), 16-bit shifter,
two data-address generators, and a program
sequencer, it used external memory for program
and data storage. Operating at 8 MHz, it dissipated
600 mW. In a single clock cycle it could: generate the
next program address; fetch the next instruction;
perform one or two data moves; update one or
two data address pointers; and perform a computational operation.
Over the intervening twenty years, digital signal processors have gotten
smaller, faster, less expensive, more powerful, and more eficient—and
they integrate up to 24 Mbits of on-chip memory. Even more important,
perhaps, are the host of peripherals that can be found on modern embedded
processors. The ADSP-BF537 Blackin processor, for example, includes
an IEEE 802.3-compliant 10/100 Ethernet medium access controller,
Controller Area Network (CAN) 2.0B interface, parallel peripheral
interface (PPI) supporting ITU-R 656 video data formats, and dual-
channel, full-duplex synchronous ports (SPORT) supporting eight
stereo I
2
S channels. The ADSP-21367 SHARC processor’s digital audio
interface (DAI) includes an S/PDIF digital audio receiver/transmitter,
8-channel sample-rate converter, sixteen pulse-width modulators, four
PLL clock generators, eight serial ports, and ROM-based audio decoder
and post-processor algorithms. The ADSP-TS201 TigerSHARC processor
includes an 8-Gbps 64-bit external port, 14-channel direct memory-access
(DMA) controller, and four 8-Gbps bidirectional link ports. Together they
provide unparalleled interface capabilities without the use of any additional
external glue logic.
Processing power and peripherals have created opportunities for digital
signal processors in diverse applications—including professional audio
mixing consoles,
always-on
cell-phone coverage, home-theater surround
sound, ingerprint recognition, network music players, wireless video,
satellite radio, and 3D motion tracking. Some of these are described
below. Details about these applications and many more can be found at
http://www.analog.com/processors/news/customerstories.
The TigerSHARC processor is the only processor capable of implementing
a software-deined digital baseband for 3G base stations, allowing the
same platform to be easily adapted for use in multiple regions—and to be
easily upgraded to support new capabilities. The TigerSHARC processor
is also the irst to implement an all-software physical layer for IEEE 802.16
WiMAX broadband wireless modems. Its best-in-class I/O bandwidth and
scalable architecture allow OEMs to differentiate their products through
advanced techniques, such as smart antennas using space-time coding and
adaptive beam-forming.
The 32-bit loating-point SHARC processor has the necessary speed and
eficiency to handle the complex post-processing algorithms required to
deliver 6.1 discrete channels of surround sound from any audio material,
allowing listeners to take full advantage of their home-theater speaker
systems, even when listening to VHS tapes, FM radio broadcasts, or
stereo music CDs. The SHARC processor’s digital audio interface, large
memory array, and VisualDSP++ graphical system design and development
environment combine to allow manufacturers to base multiple products
with various I/O requirements on a single hardware design, fully leveraging
their design time and development costs.
Blackfin processors provide both control functions and multimedia
processing capabilities, enabling diversity receivers to operate in harsh
weather and low light conditions. Providing fast information transfer,
these receivers allow soldiers, police oficers, and ireighters in the
ield to exchange audio, video, and data from sources such as cameras,
microphones, and global-positioning systems (GPS)—increasing personnel
safety in environments that are subject to high levels of interference. The low
power consumption and dynamic power management inherent in Blackin
processors is crucial for their successful use in compact, portable, battery-
powered equipment.
www.analog.com/analogdialogue
dialogue.editor@analog.com
Analog Dialogue
is the free technical magazine of Analog Devices, Inc., published
continuously for 39 years—starting in 1967. It discusses products, applications,
technology, and techniques for analog, digital, and mixed-signal processing. It is
currently published in two editions—
online
, monthly at the above URL, and quarterly
in print
, as periodic retrospective collections of articles that have appeared online. In
addition to technical articles, the online edition has timely announcements, linking to
data sheets of newly released and pre-release products, and “Potpourri”—a universe
of links to important and rapidly proliferating sources of relevant information and
activity on the Analog Devices website and elsewhere. The
Analog Dialogue
site is,
in effect, a “high-pass-iltered” point of entry to the
www.analog.com
site—the
virtual world of
Analog Devices
. In addition to all its current information, the
Analog Dialogue
site has archives with all recent editions, starting from Volume 29,
Number 2 (1995), plus three special anniversary issues, containing useful articles
extracted from earlier editions, going all the way back to Volume 1, Number 1.
If you wish to subscribe to—or receive copies of—the print edition, please go to
www.analog.com/analogdialogue
and click on
<subscribe>
. Your comments
are always welcome; please send messages to
dialogue.editor@analog.com
or to these individuals:
Dan Sheingold
, Editor
[dan.sheingold@analog.com]
or
Scott Wayne
, Managing Editor and Publisher
[scott.wayne@analog.com].
Scott Wayne
[
scott.wayne@analog.com
]
ISSN 0161-3626 ©Analog Devices, Inc. 2005
A Smart Modem for Robust Wireless
Data Transmission Over ISM Bands
(433 MHz, 868 MHz, and 902 MHz)
This need to retransmit corrupted packets is not particularly
onerous for a low-throughput system—one that sends a burst of
data from a remote sensor once every few minutes, for example.
But it does become a problem for applications such as wireless
audio or video transmission, with their higher data rates,
since the latency introduced by ARQ might be unacceptable.
It also introduces problems in industrial process-control and
telemetry systems, which must maintain throughput in a noisy
environment without the need for many retransmissions. Such
longer associated transmission times also increase the overall
system power consumption.
A powerful solution to this dilemma lies in the use of
forward
error-correction
(FEC) techniques, able to detect and correct
errors over a large enough number of bits to compensate for
partial packet loss and ensure service quality. A low-cost, yet
powerful, processor such as the
Blackin
®
4
ADSP-BF531
5
can
be used to implement intensive error-correction techniques
requiring
millions of instructions per second
(MIPS)—convolutional
coding with bit-scrambling and interleaving, for example—to
deliver a data rate of over 100 kbps with a transmission error
rate of less than 10
–6
.
When used in conjunction with the ADF7020 ISM-band transceiver
IC, with its typical range of several hundred meters (line of sight),
this approach provides a robust solution for designers wanting to
replace their current wire-line solutions without compromising
quality of service. Thanks to its 400-MIPS (
million instruction-per-
second
) and 800-MMACS (
million multiply-accumulate-per-second
)
capabilities, the ADSP-BF531 can also accommodate protocols to
support various wireless conigurations and topologies, including
point-to-point, multi-point, and broadcast, as well as sophisticated
encryption and source coding and decoding algorithms such as
Motion JPEG (MJPEG).
Figure 1 is a detailed circuit diagram of a wireless digital modem
built around the ADF7020 ISM-band transceiver and its
companion controller, the ADSP-BF531. The two main chips share
the same power supply voltage (2.3 V<V
CC
<3.6 V), and they are
By Patrick Butler [
patrick.butler@analog.com
]
Austin Harney [
austin.harney@analog.com
]
In the last few years, radio-frequency technology has advanced
by leaps and bounds, resulting in a phenomenal number of new
wireless applications. Most of these applications—
Bluetooth
®
,
1
WLAN 802.11b
,
2
and cordless telephones, for example—are
appearing alongside the microwave oven in the license-free UHF
band at 2.4 GHz. Because of the heavy trafic in the 2.4-GHz
band, and its associated co-existence issues, interest has increased
in the ISM (industrial, scientiic, medical) UHF bands—available
at the lower frequencies of 868 MHz and 433 MHz in Europe,
and 902 MHz to 928 MHz in the United States.
Unlike at 2.4 GHz, however, there is no common global standard
for the lower-UHF bands; this means that a manufacturer’s system
would have to be adaptable to each region’s regulations. However,
this burden has been eased considerably by the introduction of
lexible ISM-band transceivers, such as the
ADF7020
,
3
which
allow operation from 433 MHz to 960 MHz.
Unfortunately, one cannot entirely eliminate the problem of
interference and co-existence by simply switching to these lower-
UHF bands. As might be expected, there are plenty of legacy
systems already operating in these bands. In wireless systems,
data will be corrupted if an interferer collides with the wanted
signal—resulting in an insuficient signal-to-noise ratio (SNR)
at the receiver. A traditional way of dealing with this problem is to
use some sort of error-detection technique, e.g.,
cyclic redundancy
checking
(CRC). CRC can detect this corruption to a certain extent
and trigger the retransmission of erroneous packets (this is usually
called
automatic repeat request
, ARQ), but at the cost of considerable
delay and loss of performance in real-time applications.
L5
L4
+V
DD
100nF
100nF
100nF
100nF
100nF
D1
C10
XTAL2
32kHz
100nF
22pF
22pF
100nF
CP1
CP2
XTAL1
V
DD
EXT V
DD
RTC RTXI RTXO CLKIN
CLK
OUT
V
DD
1R
LNA
R
SET
V
DD
2
V
DD
3
V
DD
4
V
DD
OSC1
OSC2
L2
VRO
V
DD
INT
BF
FILTER
C5
L1
ADSP-BF531
400MHz
52KB SRAM
ADF702x
ISM
TRANSCEIVER
433/868/915MHz
FL0
SLE
100
F
10nF
RF
IN
FL1
SDATA
C6
FL4
SREAD
RF
IN
FL3
SCLK
UART
L3
RFSO
INT/LOCK
FL5
MUXOUT
RF
IN
B
C7
FL6
CE
R12
CP
OUT
DROPRI
DTOPRI
RCLKO
SPORT0
R11
C13
C12
Tx/Rx DATA
C11
SPORT1
RxCLK
VCO_IN
C
VCO
ADC_IN
22nF
V
REG
1
V
REG
2
V
REG
3
V
REG
4
GND1
GND2
GND5 GND4
SPI
EXTERNAL BUS
V
E
C1
C2
C3
C4
C1, C2, C3, C4 = 100nF X7R
XTAL1: 10MHz TO 12MHz
2.5V < V
DD
TYPICAL < 3.3V
SERIAL
EEPROM
(BOOT)
OPTIONAL
SDRAM
Figure 1. Circuit diagram of the modem.
Analog Dialogue Volume 39 Number 1 3
directly connected for
control
operations, using the ADSP-BF531
lags (digital I/Os) and
transmit/receive
operations, using one of
the serial synchronous ports (SPORT0).
Data will be transmitted to—or received from—the modem,
either asynchronously over the UART or synchronously with the
remaining SPORT.
regulations—but it is also possible to operate on a single channel
in the US band if the output power is below –1.5 dBm.
The high-resolution fractional-N synthesizer also forms part of a
novel
automatic frequency-control
(AFC) loop, which compensates
for incoming frequency errors and allows lower-tolerance, less-
expensive, crystals to be used. The block diagram of the ADF7020
is shown in Figure 2. The PLL loop ilter components can be
determined with the help of the
ADIsimPLL
9
simulation software,
available on the Analog Devices website.
A Versatile Transceiver
The ADF7020 is a complete monolithic radio transceiver
built using 0.25-m CMOS technology. It is capable of
operating in the 433-MHz and 868-MHz European ISM
bands (
ETSI EN300 220-1 standard
),
6
and the North American
902-to-928-MHz band—covered by
FCC Part 15 regulations
.
7
Requiring few external components and offering a high degree
of lexibility, it allows the user to conigure the part for speciic
applications. For example, there is a choice among different
modulation schemes, such as FSK, GFSK, ASK, and OOK. The
user can also trade off between sensitivity and selectivity—a useful
approach for systems that have tough linearity requirements. The
maximum data rate for the ADF7020 is 200 kbps; its sister part,
the
ADF7025
,
8
has an even greater data rate: 384 kbps.
Like most recent ISM-band transceivers, the ADF7020 utilizes a
fractional-N phase-locked-loop (PLL) synthesizer, which allows
the selection of the channels at 433 MHz, plus any channel
between 868 MHz and 928 MHz, with a resolution better than
1 kHz. This frequency agility allows the ADF7020 to be used in
frequency-hopping systems—as speciied in the US FCC Part 15
Forward Error-Correction with the Blackin Processor
While the use of a really high-performance processor in
conjunction with a radio is common in digital cellular systems, it
might at irst glance seem inappropriate for meeting the goal of a
low-cost digital modem. Implementing FEC operations at several
hundred kilobits per second, however, requires computationally
intensive digital signal-processing power comparable to that
provided by the Blackin ADSP-BF531. While a standard 8051 or
ARM-based microcontroller, for example, can adequately handle
the user interface, protocol stack, RF transceiver supervision,
and power sequencing, it would not have the computation
“horsepower” required for the FEC scheme. In addition to
implementing the control functions, the computing power and
real-time capabilities of the ADSP-BF531 allow it to: increase
the effective channel data rate, reduce communication latency,
compensate for channel propagation variations to maintain link
quality, and ensure communication security.
RSET
CREG(1:4)
ADC INPUT
MUX OUT
TEMP
SENSOR
RLNA
BIAS
LDO(1:4)
TEST MUX
OFFSET
CORRECTION
LNA
LPF
FSK/ASK
DEMODULATOR
DATA
SYNCHRONIZER
RF
IN
RF
IN
B
MUX
BB
FILTER
RSSI
7-BIT ADC
GAIN
LPF
OFFSET
CORRECTION
CE
RxCLK
AGC
CONTROL
Tx/Rx
CONTROL
Tx/Rx DATA
FSK MOD
CONTROL
GAUSSIAN
FILTER
-
MODULATOR
XCLK OUT
AFC
CONTROL
INT/LOCK
DIVIDERS/
MUXING
DIV P
N/N+1
PA OUT
SLE
SDATA IN
SERIAL
PORT
SDATA OUT
SCLK
VCO
CP
PFD
CLK
DIV
RING
OSC
DIV R
VCO IN CP OUT
XTAL
CLK OUT
Figure 2. Functional block diagram of the ADF7020.
4 Analog Dialogue Volume 39 Number 1
DSP_Tx
RF TRANSMITTER
BLOCK
INTERLEAVING
+
RATE CONTROL
INPUT OR
JPEG SOURCE
CODING
PACKETIZATION
CRC
CONVOLUTIONAL
ENCODER
MODULATION
(GFSK)
CHANNEL CODING
NOISE DISTURBANCES
TRANSMISSION
CHANNEL
FEEDBACK/QoS
DSP_Rx
DATA
DEMODULATION
(GFSK)
SYNCHRONIZATION
OUTPUT OR
JPEG SOURCE
DECODING
DE-PACKETIZATION
CRC
VITERBI
DECODER
BLOCK
DEINTERLEAVER
SYNC
RF RECEIVER
CHANNEL DECODING
Figure 3. Signal-processing functions.
Figure 3 illustrates the various functions to be carried out across
the transmission channel, including processing functions handled
for both
transmit
(Tx) and
receive
(Rx) operations. The Blackin
processor, when sitting on the transmitter side handles both
data-rate control and data partitioning, so data is transmitted in
packets at a quasi-constant rate. The data packets are processed
for forward error-correction (FEC) before they modulate the
carrier’s frequency. This is achieved by adding redundant bits
that the receiver will use to detect and correct errors. The bits
added to the incoming packets will, of course, increase the required
bandwidth for a given information bit rate.
Among the different applicable methods of FEC,
convolutional
coding
, while quite simple to implement, gives good protection
against channel Gaussian noise disturbances and helps meet
minimum Hamming-distance criteria. A convolutional encoder
is a inite state-machine comprising an L-stage shift register,
N modulo-2 adders, and a multiplexer to convert the output into
a serial bit stream. The connections between the shifter outputs
and the adder inputs determine the polynomial code. Using two
speciically applicable instructions, the Blackin core performs all
these operations very eficiently.
At the other end of the transmission channel, the decoder section
implements the Viterbi algorithm (hard-input/hard-output). For
maximum likelihood decoding, the Viterbi decoder compares all
the possible code sequences to the received code vector. The code
sequence whose Hamming distance from the received sequence
is the shortest is the good one. For a code like (1/2, 7, 371, 247)
with a constraint length, K = L + 1 of 7, the decoder can correct
up to six consecutive erroneous bits. Depending upon the system
requirements, constraint lengths (K) from 5 to 9 must be supported
by the ADSP-BF531 in such wireless applications.
However, even a convolutional code with a constraint length of 9
does not protect against burst noise that might hit the transmitted
packets over a longer length of time. The use of a complementary
protection technique based on temporal diversity is mandatory.
Temporal diversity
, i.e., spreading the bits or symbols out over time,
improves the performance of a coded communication system in the
presence of multiple paths, fading, and burst noise. It thus reduces
the probability of a consecutive number of bits being corrupted.
Scrambling and simple block interleaving functions achieve this
objective without employing more complex corrective codes (like
Reed-Solomon). Here again, the ADSP-BF531 is helpful with
two speciic vector instructions—one that computes the Viterbi
trellis butterlies and one that reconstructs data for the path-search
(trace-back) operation.
This encoded data is then passed on to the ADF7020
transmitter section, which does some additional iltering and
Gaussian frequency-shift-keying (GFSK) modulation. GFSK
modulation has the advantage of reducing the occupied spectral
bandwidth—a helpful operation when seeking to meet adjacent-
channel requirements for the European 868-MHz bands.
On the receiver side, the ADF7020’s internal preamble-matching
circuitry helps to fulill the critical packet-synchronization
task. This hardware function permits the recognition or
identiication of a 12-, 16-, 20-, or 24-bit-long programmable
synchronization word, or a packet preamble, without the
intervention of the ADSP-BF531 core. Upon a valid preamble
match, the circuitry asserts the ADF7020 INT/LOCK pin,
which signals the beginning of a new packet to the serial port
(RFS0) and triggers the Viterbi decoder. This unique circuitry
is somewhat error-tolerant—in a sense, it even allows a valid
match for up to three incorrect bits. This reduces the number
of packets lost due to preamble misses, as the preamble is not
encoded and is therefore not protected. To further reduce
preamble misses, the receiver uses one of the ADSP-BF531
32-bit timers as a watchdog that generates the expected pulse
on RFS0 if the INT/LOCK signal does not show up after a
few symbols. This use of a hardware mechanism to retrieve
packet synchronization markers was chosen in order to save
a lot of processor MIPS—compared to a full implementation
with software analysis and tracking.
Real-World Application—Wireless Video Over ISM
As noted earlier, efficient wireless digital-video transmission
calls for robustness against channel failures. Video codecs
are excellent candidates for applications with smart, reliable
Blackfin processor-based wireless modems. Given the
limitation of the ISM wireless channel bandwidth, a relatively
high image/video compression ratio is required in order to
deliver the expected frame rate and quality for a given image
size without too much latency. Unfortunately, Motion JPEG
and other video codecs require a very low transmission-error
rate, typically 10
–6
, because the source-coding process removes
most of the redundant information. This is particularly true
with some efficient entropy coders, such as Huffman, where
a single erroneous bit makes the original data impossible
to decode. A required bit-error rate (BER) less than 10
–6
places very stringent requirements on the radio, but it can
be achieved by using a channel coding scheme like the one
described above.
Analog Dialogue Volume 39 Number 1 5
Plik z chomika:
TirNaNog
Inne pliki z tego folderu:
volume1-number3(1).pdf
(7733 KB)
volume1-number2(1).pdf
(3887 KB)
volume10-number2(1).pdf
(3533 KB)
volume10-number1(1).pdf
(3227 KB)
volume1-number1(1).pdf
(1913 KB)
Inne foldery tego chomika:
ACE
AcornUser
AmigaComputing
AmigaFormat
AmigaShopper
Zgłoś jeśli
naruszono regulamin