volume39-number3(1).pdf

A forum for the exchange of circuits, systems, and software for real-world signal processing

Volume 39, Number 3, 2005

In This Issue

Editors’ Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

A Practical Guide to High-Speed Printed-Circuit-Board Layout . . . . . . . . . . . . . . . . . . . 3

Authors and Product Introductions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

40th Anniversary Timeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Direct Digital Synthesis (DDS) Controls Waveforms in Test, Measurement,

and Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Encoder’s Spare Channel Embeds Whole-House Stereo Audio in Satellite

Set-Top-Box Designs Stably and Cost-Effectively . . . . . . . . . . . . . . . . . . . . . . . . . . 16

ÜÜÜ°>>}°VÉ>>}`>}Õi

Editors’ Notes

40 TH ANNIVERSARY

We’re still celebrating the 40 th anniversary

of Analog Devices, Inc. Such events create

a temptation to wax historical, and this is no

exception. If you’re interested in the high points

of our history, the spread on pages 10-11 depicts

the contents page of a timeline accessible

on the Web (www.analog.com/timeline); in

it you can click on any year to access a brief

audiovisual clip reviewing that year’s major

corporate events.

As part of the celebration, we’ve devoted this year’s four print

issues to articles with principal technological focus on (1) digital,

(2) conversion, (3) analog, and (4) sensors. This issue is devoted

to articles discussing aspects of analog technology. As you will see,

even digital phenomena are analog at the hardware level.

600

100

400

200

AD8556

–200

NONENHANCED FOR EMI

–400

–600

–800

–1000

NONENHANCED PART

AD8556 (ENHANCED PART FOR EMI)

–1200

–20

–1400

200

400

600

800

1000

1200

200

400

600

800

1000

1200

FREQUENCY (MHz)

More about the AD8556: specified with 10-V max offset

voltage, 65-nV/C max offset drift, and 112-dB typical common-

mode rejection, it features digitally programmable gain (from

70 mV/mV to 1280 mV/mV) and output-offset voltage, open- and

short-circuited-wire fault detection, low-pass ﬁltering, EMI

ﬁltering, and output voltage clamping. Output offset voltage

can be adjusted with 0.39% resolution. Gain and offset can be

temporarily programmed by the user and evaluated in-circuit,

then permanently programmed by blowing polysilicon fuse

links. The AD8556 operates on a single 2.7-V to 5.5-V supply and

consumes 2 mA. Speciﬁed from –40C to +140C, it is available in

8-lead SOIC and 16-lead, 3-mm  3-mm LFCSP packages.

Dan Sheingold [dan.sheingold@analog.com]

RFI AGAIN—GONE!

On multiple occasions, we’ve referred to—or had our attention

called to—the dc offset problems caused by common-mode RF

interference with low-frequency measurements, particularly as

manifested by rectiﬁcation in the input stages of instrumentation

ampliﬁers. 1,2,3

Our purpose for bringing this subject up again is to mention

the availability, since July 2005, of a digitally programmable

instrumentation ampliﬁer that contains an intrinsic solution to the

problem. The AD8556, 4 designed for automotive and industrial

applications, features internal electromagnetic-interference (EMI)

ﬁltering; in addition, it has a very wide temperature range, low-offset

voltage and drift, and open- and shorted-wire protection. It can

provide a complete signal processing path from a bridge sensor to

an A/D converter. Typical applications are with pressure sensors

in anti-lock brake systems (ABS), occupant detection systems,

fuel level sensors, transmission controls, and precision strain or

pressure gauges.

The ﬁgure below shows where the on-chip EMI ﬁlters are applied

to protect the device’s inputs: at the main differential inputs, at the

clamp input, and at the input of the output ampliﬁer. In brief, the

problem that they solve is to ﬁlter out high frequencies before they

reach the ampliﬁer input junctions and create dc offsets through

partial rectiﬁcation. 5

1 “Ask The Applications Engineer—14”

http://www.analog.com/library/analogdialogue/Anniversary/14.html

Ask The Applications Engineer , Analog Devices

http://www.analog.com/library/analogdialogue/Anniversary/contents.html

2 “A Reader Notes” http://www.analog.com/library/analogdialogue/Anniversary/

Reader_Notes.html

3 H.R. Gelbach, “A Reader Notes: High-Frequency-Caused Errors in Millivolt

Measurement Systems,” Analog Dialogue 37-3, 2003, pp. 2, 14.

http://www.analog.com/library/analogdialogue/archives/issues/vol37n3.pdf

4 http://www.analog.com, Search <AD8556>

5 W. Jung, ed., “ Op Amp Applications Handbook ”, Elsevier-Newnes, 2005,

pp. 719-726. Similar material can be found online in the Analog Devices

seminar version, http://www.analog.com/library/analogdialogue/archives/

39-05/Web_Ch7_ﬁnal_J.pdf, pp. 7.122-7.129.

THE ANALOG WORLD

In mixed-signal systems, an analog-to-digital

converter (ADC) translates real-world analog

signals into the digital domain so that further

signal processing can be implemented by the

DSP or embedded processor. A digital-to-

analog converter (DAC) then translates the

digital signals back into the analog domain.

At the start of the chain, and at the end of the

day, the signals that we transmit, measure,

and control are analog: audio, video,

temperature, pressure, voltage, and current, for instance.

Some amount of analog signal conditioning is always required before

the ADC and after the DAC. Even functions that may at ﬁrst appear

to be digital are often analog at their very heart. Take phased-lock

loops (PLLs), for example. These include phase detectors, ﬁlters,

and oscillators—all analog functions. Direct digital synthesis

(DDS) devices, on the other hand, are mostly digital, but they

provide output signals whose properties are measured using analog

quantities such as phase, frequency, and amplitude.

When designing analog circuitry—especially where high speed,

high resolution, or low noise is required—a good printed-circuit

board layout becomes increasingly important. Careful attention

to voltage levels and signal ﬂow can minimize the need for an

expensive, time-consuming redesign, and can maintain optimum

performance throughout the signal path.

With all this in mind, we invite you to read the “analog” installment

of Analog Dialogue’ s tribute to ADI’s 40 th anniversary. Here you

will learn about adding stereo audio to a low-cost satellite set-top

box; using DDS to generate waveforms for test, measurement,

and communications; and avoiding the layout pitfalls inherent in

high-speed ampliﬁer designs. Enjoy!

Scott Wayne [scott.wayne@analog.com]

DIGIN

VDD

VCLAMP

LOGIC

DAC

VDD

EMI

FILTER

+IN

–IN

EMI

FILTER

VPOS

+IN

–IN

OUT

VSS

VDD

EMI

FILTER

+IN

–IN

EMI

FILTER

+IN

–IN

OUT

V OUT

OUT

VDD

VSS

+IN

–IN

VSS

OUT

EMI

FILTER

VNEG

AD8556

VSS

FILT/DIGOUT

The effectiveness of this filtering scheme can be seen in the

figures at the top of next column, comparing responses of the

AD8556 and the AD8555, a similar device—but without internal

EMI protection. The graph at left compares their dc responses to

200-mV common-mode high-frequency signals that drive both

differential inputs (G = 70 mV/mV). The one at right measures

dc output responses to 200-mV p-p of high-frequency sine waves

driving VPOS, with VNEG grounded.

ISSN 0161-3626 ©Analog Devices, Inc. 2005

A Practical Guide to High-Speed

Printed-Circuit-Board Layout

By John Ardizzoni [john.ardizzoni@analog.com]

ground, analog, digital, and RF); which signals need to be on each

layer; where the critical components need to be located; the exact

location of bypassing components; which traces are critical; which

lines need to be controlled-impedance lines; which lines need to

have matched lengths; component sizes; which traces need to kept

away from (or near) each other; which circuits need to be kept away

from (or near) each other; which components need to be close to (or

away from) each other; which components go on the top and the

bottom of the board. You’ll never get a complaint for giving someone

too much information—too little , yes; too much, no.

Despite its critical nature in high-speed circuitry, printed-circuit-

board (PCB) layout is often one of the last steps in the design

process. There are many aspects to high-speed PCB layout;

volumes have been written on the subject. This article addresses

high-speed layout from a practical perspective. A major aim is to

help sensitize newcomers to the many and various considerations

they need to address when designing board layouts for high-speed

circuitry. But it is also intended as a refresher to beneﬁt those

who have been away from board layout for a while. Not every

topic can be covered in detail in the space available here, but we

address key areas that can have the greatest payoff in improving

circuit performance, reducing design time, and minimizing time-

consuming revisions.

Although the focus is on circuits involving high-speed op amps,

the topics and techniques discussed here are generally applicable

to layout of most other high-speed analog circuits. When op amps

operate at high RF frequencies, circuit performance is heavily

dependent on the board layout. A high-performance circuit design

that looks good “on paper” can render mediocre performance

when hampered by a careless or sloppy layout. Thinking ahead and

paying attention to salient details throughout the layout process

will help ensure that the circuit performs as expected.

A learning experience: About 10 years ago I designed a

multilayer surface-mounted board—with components on

both sides of the board. The board was screwed into a gold-

plated aluminum housing with many screws (because of a

stringent vibration spec). Bias feedthrough pins poked up

through the board. The pins were wire-bonded to the PCB.

It was a complicated assembly. Some of the components on

the board were to be SAT (set at test). But I hadn’t speciﬁed

where these components should be. Can you guess where

some of them were placed? Right! On the bottom of the

board. The production engineers and technicians were not

very happy when they had to tear the assembly apart, set

the values, and then reassemble everything. I didn’t make

that mistake again.

Location, Location, Location

As in real estate, location is everything. Where a circuit is placed

on a board, where the individual circuit components are located,

and what other circuits are in the neighborhood are all critical.

Typically, input-, output-, and power locations are deﬁned, but

what goes on between them is “up for grabs.” This is where paying

attention to the layout details will yield signiﬁcant returns. Start

with critical component placement, in terms of both individual

circuits and the entire board. Specifying the critical component

locations and signal routing paths from the beginning helps ensure

that the design will work the way it’s intended to. Getting it right

the ﬁrst time lowers cost and stress—and reduces cycle time.

The Schematic

Although there is no guarantee, a good layout starts with a good

schematic. Be thoughtful and generous when drawing a schematic,

and think about signal ﬂow through the circuit. A schematic that

has a natural and steady ﬂow from left to right will tend to have a

good ﬂow on the board as well. Put as much useful information

on the schematic as possible. The designers, technicians, and

engineers who will work on this job will be most appreciative,

including us; at times we are asked by customers to help with a

circuit because the designer is no longer there.

What kind of information belongs on a schematic besides the

usual reference designators, power dissipations, and tolerances?

Here are a few suggestions that can turn an ordinary schematic

into a super schematic! Add waveforms, mechanical information

about the housing or enclosure, trace lengths, keep-out areas;

designate which components need to be on top of the board;

include tuning information, component value ranges, thermal

information, controlled impedance lines, notes, brief circuit

operating descriptions … (and the list goes on).

Power-Supply Bypassing

Bypassing the power supply at the ampliﬁer’s supply terminals to

minimize noise is a critical aspect of the PCB design process—both

for high-speed op amps and any other high-speed circuitry. There

are two commonly used conﬁgurations for bypassing high-speed

op amps.

Rails to ground: This technique, which works best in most cases,

uses multiple parallel capacitors connected from the op amp’s

power-supply pins directly to ground. Typically, two parallel

capacitors are sufﬁcient—but some circuits may beneﬁt from

additional capacitors in parallel.

Paralleling different capacitor values helps ensure that the

power supply pins see a low ac impedance across a wide band of

frequencies. This is especially important at frequencies where the

op amp power-supply rejection (PSR) is rolling off. The capacitors

help compensate for the ampliﬁer’s decreasing PSR. Maintaining

a low impedance path to ground for many decades of frequency

will help ensure that unwanted noise doesn’t ﬁnd its way into the

op amp. Figure 1 shows the beneﬁts of multiple parallel capacitors.

At lower frequencies the larger capacitors offer a low impedance

path to ground. Once those capacitors reach self resonance, the

capacitive quality diminishes and the capacitors become inductive.

That is why it is important to use multiple capacitors: when one

capacitor’s frequency response is rolling off, another is becoming

signiﬁcant, thereby maintaining a low ac impedance over many

decades of frequency.

Trust No One

If you’re not doing your own layout, be sure to set aside ample

time to go through the design with the layout person. An ounce of

prevention at this point is worth more than a pound of cure! Don’t

expect the layout person to be able to read your mind. Your inputs

and guidance are most critical at the beginning of the layout process.

The more information you can provide, and the more involved you

are throughout the layout process, the better the board will turn

out. Give the designer interim completion points—at which you

want to be notiﬁed of the layout progress for a quick review. This

“loop closure” prevents a layout from going too far astray and will

minimize reworking the board layout.

Your instructions for the designer should include: a brief description

of the circuit’s functions; a sketch of the board that shows the input

and output locations; the board stack up (i.e., how thick the board

will be, how many layers, details of signal layers and planes—power,

Analog Dialogue Volume 39 Number 3

This process should be repeated for the next-higher-value

capacitor. A good place to start is with 0.01 F for the smallest

value, and a 2.2-F—or larger—electrolytic with low ESR for the

next capacitor. The 0.01 F in the 0508 case size offers low series

inductance and excellent high-frequency performance.

Rail to rail: An alternate conﬁguration uses one or more bypass

capacitors tied between the positive- and negative supply

rails of the op amp. This method is typically used when it is

difﬁcult to get all four capacitors in the circuit. A drawback to

this approach is that the capacitor case size can become larger,

because the voltage across the capacitor is double that of the

single-supply bypassing method. The higher voltage requires a

higher breakdown rating, which translates into a larger case size.

This option can, however, offer improvements to both PSR and

distortion performance.

Since each circuit and layout is different; the conﬁguration,

number, and values of the capacitors are determined by the actual

circuit requirements.

��

�

��

�

��

Figure 1. Capacitor impedance vs. frequency.

Starting directly at the op amp’s power-supply pins; the capacitor

with the lowest value and smallest physical size should be placed

on the same side of the board as the op amp—and as close to the

ampliﬁer as possible. The ground side of the capacitor should

be connected into the ground plane with minimal lead- or trace

length. This ground connection should be as close as possible to

the ampliﬁer’s load to minimize disturbances between the rails

and ground. Figure 2 illustrates this technique.

Parasitics

Parasitics are those nasty little gremlins that creep into your PCB

(quite literally) and wreak havoc within your circuit. They are the

hidden stray capacitors and inductors that inﬁltrate high-speed

circuits. They include inductors formed by package leads and

excess trace lengths; pad-to-ground, pad-to-power-plane, and

pad-to-trace capacitors; interactions with vias, and many more

possibilities. Figure 3(a) is a typical schematic of a noninverting

op amp. If parasitic elements were to be taken into account,

however, the same circuit would look like Figure 3(b).

In high-speed circuits, it doesn’t take much to inﬂuence circuit

performance. Sometimes just a few tenths of a picofarad is

enough. Case in point: if only 1 pF of additional stray parasitic

capacitance is present at the inverting input, it can cause almost

2 dB of peaking in the frequency domain (Figure 4). If enough

capacitance is present, it can cause instability and oscillations.

�

��

�

Figure 2. Parallel-capacitor rails-to-ground bypassing.

��

� �

��

� �

��

� �

��

� �

��

� �

��

� �

��

� � ��

� �

��

Figure 3. Typical op amp circuit, as designed (a) and with parasitics (b).

��

Analog Dialogue Volume 39 Number 3

��

�

��

�

��

�

��

� �

��

�

��

Figure 4. Additional peaking caused by parasitic capacitance.

Figure 7. Pulse response with—and without—ground plane.

A few basic formulas for calculating the size of those gremlins

can come in handy when seeking the sources of the problematic

parasitics. Equation 1 is the formula for a parallel-plate capacitor

(see Figure 5).

Vias are another source of parasitics; they can introduce both

inductance and capacitance. Equation 3 is the formula for parasitic

inductance (see Figure 8).



 



 

(3)

L T

= 11.

(1)

T is the thickness of the board and d is the diameter of the via

in centimeters.

C is the capacitance, A is the area of the plate in cm 2 , k is the

relative dielectric constant of board material, and d is the distance

between the plates in centimeters.

��

� �

�

� �

�

Figure 5. Capacitance between two plates.

Strip inductance is another parasitic to be considered, resulting

from excessive trace length and lack of ground plane. Equation 2

shows the formula for trace inductance. See Figure 6.





W H



 

W H



  +

Inductance

00002

 

+ ( ) +

02235

 

(2)





�

W is the trace width, L is the trace length, and H is the thickness

of the trace. All dimensions are in millimeters.

�

� �

�

Figure 8. Via dimensions.

�

Equation 4 shows how to calculate the parasitic capacitance of

a via (see Figure 8).

055 1

. ε

D D

(4)

−

Figure 6. Inductance of a trace length.

 r is the relative permeability of the board material. T is the

thickness of the board. D 1 is the diameter of the pad surrounding

the via. D 2 is the diameter of the clearance hole in the ground plane.

All dimensions are in centimeters. A single via in a 0.157-cm-thick

board can add 1.2 nH of inductance and 0.5 pF of capacitance;

this is why, when laying out boards, a constant vigil must be kept

to minimize the inﬁltration of parasites!

The oscillation in Figure 7 shows the effect of a 2.54-cm trace

length at the noninverting input of a high-speed op amp. The

equivalent stray inductance is 29 nH (nanohenry), enough to

cause a sustained low-level oscillation that persists throughout the

period of the transient response. The picture also shows how using

a ground plane mitigates the effects of stray inductance.

Analog Dialogue Volume 39 Number 3

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika: