HT8955.PDF

(589 KB) Pobierz
300789243 UNPDF
HT8955A
Voice Echo
Features
·
Operating voltage: 5.0V
·
Built-in pre-amplifier
·
Long delay time
– 0.8 seconds (SEL=VSS, 256K DRAM)
– 0.2 seconds (SEL=VDD/open, 64K DRAM)
·
Low distortion
·
High S/N ratio
·
Wide frequency response
·
25kHz sampling rate
·
PCM 10-bit A/D and D/A converters
·
Continuous variable delay time
·
24-pin DIP package
Applications
·
Mixers
·
Echo generators
·
Karaoke systems
·
Sound effect generators
General Description
The HT8955A is a CMOS LSI digital audio
signal delay processor. It is designed for
audio system applications including echo
generators, karaoke systems, sound effect
generators, etc.
The chip consists of a built-in pre-amplifier,
on-chip oscillator, DRAM interface, 10-bit A/D
and D/A converters as well as control logic. It
provides continuously adjustable delay time up
to 0.8/0.2 seconds at a sampling rate of 25kHz
when combined with an external DRAM
(41256/4164). The HT8955A is superior to a
conventional BBD delay unit in its low distor-
tion, high S/N ratio and long delay time. Its
sophisticated low pass filter will not end in the
normal applications due to the high sampling
rate (25~50kHz). Hence, the HT8955A is excel-
lent for audio delay system applications. It is
offered in a 24-pin dual-in-line package.
Pin Assignment
Block Diagram
1
5th May ’98
300789243.059.png 300789243.070.png 300789243.081.png 300789243.092.png 300789243.001.png 300789243.010.png 300789243.011.png 300789243.012.png 300789243.013.png 300789243.014.png 300789243.015.png 300789243.016.png 300789243.017.png 300789243.018.png 300789243.019.png 300789243.020.png 300789243.021.png 300789243.022.png 300789243.023.png 300789243.024.png 300789243.025.png 300789243.026.png 300789243.027.png 300789243.028.png 300789243.029.png 300789243.030.png 300789243.031.png 300789243.032.png 300789243.033.png 300789243.034.png 300789243.035.png 300789243.036.png 300789243.037.png 300789243.038.png 300789243.039.png 300789243.040.png 300789243.041.png 300789243.042.png 300789243.043.png 300789243.044.png 300789243.045.png 300789243.046.png
HT8955A
Pad Coordinates
Unit:
m
m
Pad
No.
X
Y
Pad
No.
X
Y
1 –1138.00 796.50 14 1141.50 –547.00
2 –1141.00 523.50 15 1141.50 –197.50
3 –1136.50 201.50 16 1141.50 111.50
4 –1136.50 –163.00 17 1141.50 461.00
5 –1137.00 –507.00 18 1141.50 770.50
6 –1149.00 –774.00 19 896.00 811.00
7 –854.50 –853.50 20 645.00 810.50
8 –548.00 –831.50 21 435.00 794.00
9 –198.50 –831.50 21 335.00 794.00
10 111.50 –831.50 22 150.00 779.00
11 461.00 –831.50 23 –35.00 779.00
12 773.00 –831.50 25 –264.00 806.00
13 1122.50 –831.50
Chip size: 2170
´
2200 (
m
m) 2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pin Description
Pin No. Pin Name I/O
Internal
Connection
Description
1
BIAS
O OP Non-inverted
Internal pre-amplifier bias
Connects to a decoupling capacitor
2
IN
I
OP Inverted
Audio signal input pin (inverted)
3
PREO
O
OP OUTPUT
Pre-amplifier output pin
4
OUT
O
—
Delayed audio signal output pin
5
SEL
I
Pull-High
DRAM type selection:
VDD or Open: 64Kb
VSS: 256Kb
6
OSC1
I
—
System oscillator input
7
OSC2
O
—
System oscillator output
8
OSC3
I
—
Delay time control oscillator input
9
OSC4
O
—
Delay time control oscillator output
10
VSS
I
—
Negative power supply (GND)
11
A6
O
CMOS OUT
Connects to DRAM A6
12
A7
O
CMOS OUT
Connects to DRAM A7
2
5th May ’98
300789243.047.png 300789243.048.png 300789243.049.png 300789243.050.png 300789243.051.png 300789243.052.png 300789243.053.png 300789243.054.png 300789243.055.png 300789243.056.png
HT8955A
Pin No. Pin Name I/O
Internal
Connection
Description
13
A5
O
CMOS OUT
Connects to DRAM A5
14
A4
O
CMOS OUT
Connects to DRAM A4
15
A3
O
CMOS OUT
Connects to DRAM A3
16
A2
O
CMOS OUT
Connects to DRAM A2
17
A1
O
CMOS OUT
Connects to DRAM A1
18
A0
O
CMOS OUT
Connects to DRAM A0
19
RASB
O
CMOS OUT
Connects to DRAM RASB
20
WRB
O
CMOS OUT
Connects to DRAM WRB
21
DATA
I/O
CMOS I/O
Data I/O pin
22
A8
O
CMOS I/O
Connects to DRAM A8
23
CASB
O
CMOS I/O
Connects to DRAM CASB
24
VDD
I
—
Positive power supply
Absolute Maximum Ratings*
Supply Voltage ................................. –0.3V to 6V
Storage Temperature................. –50
°
C to 125
°
C
Input Voltage................. V SS –0.3V to V DD +0.3V
Operating Temperature............... –20
°
C to 70
°
C
*Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maxi-
mum Ratings” may cause substantial damage to the device. Functional operation of this
device at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.
Electrical Characteristics
(Ta=25
°
C)
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
V DD
Conditions
V DD
Operating Voltage
—
—
4.5
5.0
5.5
V
I OP
Operating Current
5V
No load,
f OSC =640kHz
—2.5
8
A
V Pre-amplifier Voltage Gain 5V
W
Open loop
—0—/V
V Comparator Voltage Gain
5V
W
Open loop
—0—/V
IL
“L” Input Voltage
—
—
0
— 0.3V DD V
3
5th May ’98
R L >100k
R L >100k
300789243.057.png
HT8955A
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
V DD
Conditions
V IH
“H” Input Voltage
—
—
0.7V DD
— DD
V
V OMAX Maximum Output Voltage
5V R L >470k
W
1
1.5
—V
Td
5V
SEL=open, 25kHz
sampling rate
0.15
0.2
—
s
Maximum Delay Time
SEL=VSS, 25kHz
sampling rate
Td
5V
0.6
0.8
—
s
S/N
Signal to Noise Ratio
5V
V O =1V, 400Hz
BW=10kHz
—55
—dB
THD
Total Harmonic Distortion
5V
V O =1V, 400Hz
BW=7kHz
—0.5
—%
Functional Description
The HT8955A is a single chip LSI with an exter-
nal DRAM. It is designed for processing audio
signal delay. The chip includes a built-in pre-
amplifier, 10-bit A/D and D/A converters. The
A/D and D/A converters ensure low distortion as
well as high S/N ratio of the audio delay system.
The chip also provides two sets of oscillation
circuit for system sampling rate and audio echo
delay time.
demands an external resistor between the
OSC3 and OSC4 pins. By altering the oscilla-
tion resistor, its delay time can be continuously
adjusted up to 0.8/0.2 seconds at a 25kHz sam-
pling rate for DRAM of 256Kb/64Kb.
Playing function block diagram
DRAM selection
The HT8955A can interface with a DRAM for
storing delay signals. The type along with the
maximum delay time of DRAM is determined
by the status of the SEL pin as shown:
System oscillator
The HT8955A provides two oscillators, one for
the sampling rate and one for echo delay time.
The sampling rate oscillator requires an exter-
nal resistor between the OSC1 and OSC2 pins.
A higher sampling rate (25~50kHz) can thus be
derived by adjusting the oscillation resistor
without having a sophisticated low pass filter.
The delay time oscillator, on the other hand,
SEL Connection
DRAM
Type
Delay Time
VDD or Open
64Kb
0.2 seconds
VSS
256Kb
0.8 seconds
4
5th May ’98
300789243.058.png 300789243.060.png 300789243.061.png 300789243.062.png 300789243.063.png 300789243.064.png 300789243.065.png 300789243.066.png 300789243.067.png 300789243.068.png 300789243.069.png
HT8955A
Application Circuits
Low cost echo
5
5th May ’98
300789243.071.png 300789243.072.png 300789243.073.png 300789243.074.png 300789243.075.png 300789243.076.png 300789243.077.png 300789243.078.png 300789243.079.png 300789243.080.png 300789243.082.png 300789243.083.png 300789243.084.png 300789243.085.png 300789243.086.png 300789243.087.png 300789243.088.png 300789243.089.png 300789243.090.png 300789243.091.png 300789243.093.png 300789243.094.png 300789243.095.png 300789243.096.png 300789243.097.png 300789243.098.png 300789243.099.png 300789243.100.png 300789243.101.png 300789243.102.png 300789243.002.png 300789243.003.png 300789243.004.png 300789243.005.png 300789243.006.png 300789243.007.png 300789243.008.png 300789243.009.png

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin