SL 2001.pdf

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DVD BACK PANEL BOARD
 
DVD-FRONT PANEL
DVD SMPS 002
 
STANDBY voltages still carry power durin
g Standby Mode
VCC-STANDBY
VCC3-STANDBY
J11
J12
Reserv ed for SPDIF input
+12V
-12V
+5V
1
1
#BPRESET
#BPRESET
1
1
2
2
2
2
3
3
SPDIF
SPDIF
3
3
4
4
4
4
5
5
SPDIF_IN
5
5
6
6
6
6
7
7
PCMCLK
PCMCLK
7
VIDFILTR
7
8
8
8
8
9
9
SCLK
RED
RED_OUT
SCLK
9
RED
RED
GREEN
BLUE
CHROMA
LUMA
CVBS
RED_OUT
GREEN_OUT
BLUE_OUT
CHROMA_OUT
LUMA_OUT
CVBS_OUT
9
10
10
LRCLK
LRCLK
10
10
11
11
SDATA0
GREEN
GREEN_OUT
SDATA0
SDATA1
11
GREEN
BLUE
11
12
12
SDATA1
12
12
13
13
SDATA2
BLUE
CHROMA
BLUE_OUT
SDATA2
13
13
14
14
14
14
15
15
BPPIO0
CHROMA_OUT
BPPIO0
15
CHROMA
LUMA
15
16
16
BPPIO1
BPPIO1
16
16
17
17
BPPIO2
LUMA
LUMA_OUT
BPPIO2
17
17
18
18
BPPIO3
BPPIO3
18
18
19
19
SCL
CVBS
CVBS_OUT
SCL
19
CVBS
19
20
20
SDA
20
20
SDA
{Value}
FFC20
FFC20
VCC-PCM
C90
R59
562R
1%
U13
8
AOUTL
10uF
16V
4
R60
100K
1%
C91
MCLK
JP11
2
SCLK
1500pF
3
R145
75R
CVBS
LEFT
RIGHT
LRCLK
6
1
SDATA
5
AOUTR
C92
R61
562R
1%
CS4334
C145
47pF
10uF
16V
R62
100K
1%
C93
HEADER 6
1500pF
STI5505 - Back Panel Connectors
 
MA[0..11]
ADR[1..20]
DATA[0..15]
MA[0..11]
ADR[1..20]
DATA[0..15]
MD[0..15]
MD[0..15]
VCC3-DENC
#JTAG_RESET
VCC3
VCC3
U3
1
2
VCC3-PCM
4
R7
10K
R8
10K
#POWERON_RESET
TP1
LMOS TC4S81F
U1
R9
NS
#SDCS0
84
137
#SDCS0
#SDCS1
#SDRAS
#SDCAS
#SDWE
DQML
SDCS0
PPCCLK
PPCCLK
85
#SDCS1
R10
33R
SDCS1
#SDRAS
88
DMAXFER 134
SDRAS
89
PPC_MODE 138
#SDCAS
R11
10K
SDCAS
90
135
#SDWE
SDWE
CS
91
136
DQML
#READY
DQML
READY
#READY
DQMU
1 05
DQMU
DQMU
124
#CE1
R127
33R
CE1
76
125
#CE1
SDCLK
SDCLK
MEMCLKOUT
CE2
1 04
126
#CE3
R128
33R
MEMCLKIN
CE3
#CE3
133
R/W
#BE0
R129
33R
R/W
R/W
123
#OE
VCC3
R130
33R
OE
#OE
78
121
MA0
R131
33R
AD0
BE0
#WE
MA1
79
122
AD1
BE1
80
R12
10K
TRIGIN
MA2
AD2
R13
10K
TRIGOUT
MA3
81
127
#RAS0
R132
33R
AD3
RAS0
#RAS0
R14
10K
MA4
69
128
#RAS1
R133
33R
AD4
RAS1
#RAS1
#CAS0
R15
10K
MA5
70
129
#CAS0
R134
33R
AD5
CAS0
71
132
R16
10K
MA6
#CAS1
R135
33R
AD6
CAS1
72
#CAS1
R17
10K
MA7
AD7
R18
10K
MA8
73
23
IR
AD8
IRQ0
I INT
MA9
74
25
INT
AD9
IRQ1
MA10
82
AD10
83
47
MA11
R202
33R
SPDIF
J3
AD11
SPDIF
SPDIF
92
45
MD0
R19
33R
AUDCLK
2
1
DQ0
PCM_CLK
AUDCLK
MD1
93
4
3
DQ1
94
43
MD2
R203
33R
SCLK
6
5
DQ2
SCLK
SCLK
MD3
97
46
R204
33R
LRCLK
8
7
DQ3
LRCLK
LRCLK
98
44
MD4
R205
33R
SDATA0
10
9
DQ4
PCM_OUT0
SDATA0
MD5
99
24
R206
33R
SDATA1
12
11
DQ5
PCM_OUT1
SDATA1
MD6
100
21
R207
33R
SDATA2
14
13
DQ6
PIO0_6/PCM_OUT2
SDATA2
MD7
101
16
15
DQ7
118
PIXCLK
18
17
PIXCLK _27Mhz
106
PIXCLK
MD8
20
19
DQ8
MD9
107
51
DQ9
HSYNC
TP13
TP14
MD10
108
52
HEADER20
Shrouded
DQ10
ODD/EVEN
MD11
109
117
DQ11
OSD_ACTIVE
112
MD12
DQ12
MD13
113
57
RED
BLUE
DQ13
R_OUT
RED
114
56
MD14
GREEN
DQ14
G_OUT
GREEN
BLUE
MD15
115
55
DQ15
B_OUT
R22
10K
R23
10K
#RESET
29
62
LUMA
RESET
Y_OUT
LUMA
63
CHROMA
C_OUT
CHROMA
26
JP3
PWM0/OSLINK_SEL
27
64
CVBS
PWM1/BOOTFROMROM
CVBS_OUT
28
CVBS
PWM2
JUMPER
1 88
191
TCK
R24
10K
R25
10K
R26
75R
TCK
YUV0/PIO4_0
FP_DATA
TDI
1 86
192
TDI
YUV1/PIO4_1
189
193
FP_CLK
FP_STB
TDO
R2 7
56R
TDO
YUV2/PIO4_2
TMS
1 87
194
TMS
YUV3/PIO4_3
190
195
#TRST
TRST
YUV4/PIO4_4
TP17
196
C86
47pF
YUV5/PIO4_5
TP7
TP8
TP9
TP10
16
197
PARA_REQ
PARA_SYNC
PARA_REQ/PIO0_3
YUV6/PIO4_6
PARA_REQ
PARA_SYNC
PARA_STR
15
198
PARA_SYNC/PIO0_0
YUV7/PIO1_3
17
PARA_STR
PARA_STR/PIO0_4
PARA_DVALID
33
TP15
PARA_DVALID
PARA_DATA0
PARA_DATA1
PARA_DATA2
R2 8
220R
20
PARA_DATA0/PIO0_5
R29
220R
22
5
OPEN
PARA_DATA1/PIO0_7
PIO2_3
OPEN
36
6
R30
220R
#SENSE
PARA_DATA2/B_DATA
PIO2_4
#SENSE
CLOSE
PARA_DATA3
R31
220R
37
11
CLOSE
PARA_DATA3/B_BCLK
PIO1_5/TXD1
38
12
PARA_DATA4
R32
220R
#PUSH
PARA_DATA4/B_FLAG
PIO1_6/RXD1
#PUSH
PARA_DATA5
R33
220R
39
PARA_DATA5/B_SYNC
30
7
PARA_DATA6
R34
220R
RTS
PARA_DATA6/SDAV_CLK
PIO2_5
RTS
PARA_DATA7
R35
220R
31
8
CTS
PARA_DATA7/SDAV_DATA
PIO2_7
CTS
TXD
13
PAR A_DATA[0..7]
TXD
PIO1_7/TXD3
14
RXD
PIO4_7/RXD3
RXD
PARA_DATA[0..7]
32
SDAV_VALID
10
SCL
SDA
PIO1_2/SCL
SCL
40
9
NRSS_CLK/B_WCLK
PIO1_0/SDA
SDA
42
R168
NS
TP16
NRSS_IN/B_V4
41
116
NRSS_OUT
AUXCLK
VCC
STi5505
U2
R38
4K7
1
6
A0
SCL
2
5
#RESET
A1
SDA
#RESET
3
R39
4K7
TP11
A2
R 40
18K7
R 41
11K5
7
WC
1%
1%
BPPIO0
BPPIO1
BPPIO2
BPPIO3
BPPIO0
I2C-EEPROM
256x8
BPPIO1
R42
10K
BPPIO2
BPPIO3
#SOFT_RESET
Defa ult configuration
I2C Address: 0xA0
(Write), 0xA1(Read)
SR0
C87
330pF
C88
.0033uF
SR0
FS0
FS1
R 147
10K
R 148
10K
R 149
10K
FS0
FS1
PARA_DVALID
#FERESET
R4 3
0R0
PARA_DATA6
R45
10K
#FERESET
R44
NS
#BPRESET
R4 9
0R0
PARA_DATA7
#BPRESET
R50
NS
STI5505 - Core Logic
 

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