sp601.pdf
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SP601
Semiconductor
July 1998
File Number 2429.5
Features
Half Bridge 500VDC Driver
• Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
The SP601 is a smart power high voltage integrated circuit
(HVIC) optimized to drive MOS gated power devices in half-
bridge topologies. It provides the necessary control and
management for PWM motor drive, power supply, and UPS
applications.
• Ability to Interface and Drive Standard and Current
Sensing N-Channel Power MOSFET/IGBT Devices
• Creation and Management of a Floating Power Supply
for Upper Rail Drive
• Simultaneous Conduction Lockout
• Overcurrent Protection
Ordering Information
• Single Low Current Bias Supply Operation
PART
NUMBER
TEMPERATURE
RANGE
• Latch Immune CMOS Logic
PACKAGE
• Peak Drive in Excess of 0.5A
SP601
-40
o
C to +85
o
C
22 Lead Plastic DIP
Pinout
SP601 (PDIP)
TOP VIEW
Functional Block Diagram
V
BS
12
D1U
UP/
V
BIAS
10
W
R
ND
19
FAULT
I
TRIPSEL
V
BIAS
V
DD
V
SS
TRIP
L
1
22
DOWN
G1U
2
21
20
EN-
3
I
ONT
I
OFFT
18
ABLE
V
DD
S
R
LEVEL
SHIFT
3
NC
Q
G2U
4
17
4
19
D1U
G1U
G2U
3.5
R
BS
V
DF
TRIP
U
5
18
UV
LOCK
OUT
+
-
11
15
6
17
CL1
7
16
CL2
CL2
16
PHASE
14
G2L
8
15
TRIP
U
G1L
9
14
PHASE
S
R
UP/DN
22
I
TRIPSEL
Q
D1L
10
13
V
OUT
3.5
W
R
O
V
OUT
V
DF
11
12
V
BS
13
D1L
10
ENABLE
21
I
ONB
I
OFFB
S
R
Q
G1L
9
CMOS
TIMING
AND
CONTROL
G2L
V
OUT
SENSE
AND
FILTER
8
UV
LOCK
OUT
FAULT
750
W
R
F
FAULT
TRIP
L
-
6
S
R
1
Q
CL1
7
FILTER
I
TRIPSEL
S
R
Q
I
TRIPSEL
V
SS
2
5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
W
SP601
Absolute Maximum Ratings
Full Temperature Range, All
Voltage Referenced to V
SS
Unless Otherwise Noted. Note 1, Note 2.
Thermal Information
Low Voltage Power Supply, V
BIAS
(Note 1) . . . . . . . . . . . . . . 18V
DC
Floating Low Voltage Boot Strap . . . . . . . . . . . . . . . . . . . . . . 18V
DC
Power Supply to Phase, V
BS
Low Voltage Signal Pins
Fault, I
TRIPSEL
, V
DD
, TRIP
L
, CL1, G2L. . . . -0.5V
DC
to V
DD
+0.5
G1L, D1L, V
DF
, TOP, BOT
CL2, TRIP
U
, G1U, G2U, D1U to Phase . . . . .-0.5
VDC
to V
BS
+0.5
High Voltage Pins
Phase, V
PHASE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
DC
(V
BS
,V
OUT
, TRIP
U
, CL2, G2U and D1U: 0V-18V Higher Than
Phase)
Dynamic High Voltage Rating Phase, . . . . . . . . . . . . . 10,000V/
m
s
DV
PHASE/DT
Thermal Resistance, Junction-to-Ambient
q
JA
75
o
C/W
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Package Power Dissipation at T
A
= +85
o
C, P
O
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW
Operating Ambient Temperature Range, T
A
. . . . . . .-40
o
C to +85
o
C
Storage Temperature Range, T
S
. . . . . . . . . . . . . . .-40
o
C to +150
o
C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +265
o
C
NOTES:
1. Care must be taken in the application of V
BIAS
as not to impose high peak dissipation demands on a relatively small metallized noise dropping resistor (R
ND
).
Prolonged high peak currents may result if +15V
DC
is applied abruptly and/or if the local bypass capacitor C
DD
is large. It is suggested that C
DD
be
£
10MFD.
If it is desirable to switch the 15V
DC
source or if a C
DD
is larger, additional series impedance may be required.
2. Consult factory for additional package offerings.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
(V
BIAS
= 15V, Pulsed <300ms), Unless Otherwise Noted, All Parameters Referenced to V
SS
Except TRIP
U
,
CL2, G1U, D1U, and V
BS
Referenced to PHASE. D
F
: V
DF
to V
BS
, C
F
: V
BS
to PHASE
PARAMETER
SYMBOL
TEMP
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
Input Current (5V < V
TOP
, V
BOT
, V
TRIPSEL
< 15V)
I
IN
+25
o
C
-
20
30
m
A
-40
o
C to +85
o
C
-
30
33
m
A
I
BIAS
Quiescent Current (All Inputs Low)
I
BIAS
L
+25
o
C
-
1.7
2.05
mA
-40
o
C to +85
o
C
-
1.7
2.1
mA
I
BIAS
Quiescent Current
(V
OUT
³
V
BIAS
, and All Inputs Low)
I
BIAS
H
+25
o
C
-
1.7
2.05
mA
-40
o
C to +85
o
C
-
1.7
2.1
mA
I
BS
Quiescent Current Bootstrap Supply
I
BS
+25
o
C
-
875
1000
m
A
-40
o
C to +85
o
C
-
900
1060
m
A
ENABLE Threshold Level
V
TOP
+25
o
C
7
8
9
V
-40
o
C to +85
o
C
6.95
8
9.1
V
UP/DN Threshold Level
V
BOT
+25
o
C
7
8
9
V
-40
o
C to +85
o
C
6.95
8
9.1
V
Current Trip Select Threshold Level
V
TRIPSEL
+25
o
C
7
8
9
V
-40
o
C to +85
o
C
6.95
8
9.1
V
Trip Lower and Upper Comparator Threshold
Level - Normal (I
TRIPSEL
= V
SS
)
V
TRIP L/U
N
+25
o
C
90
105
125
mV
-40
o
C to +85
o
C
90
105
127
mV
Trip Lower and Upper Comparator Threshold
Level - Boost (I
TRIPSEL
= V
DD
) % of Measured
V
TRIP L/U
N
V
TRIP L/U
B
+25
o
C
110
130
150
%
-40
o
C to +85
o
C
109
130
152
%
Under Voltage Lockout Thresholds (V
DD
and V
BS
)
V
LOCK
+25
o
C
9
10
11.5
V
-40
o
C to +85
o
C
9.7
10.5
11.8
V
Phase Out of Status Voltage Threshold (PHASE)
V
OSVT
+25
o
C
5
7
9
V
-40
o
C to +85
o
C
4.7
7
9.6
V
Faultbar Impedance at I
FBAR
= 1mA
RF
+25
o
C
500
760
1000
W
-40
o
C to +85
o
C
450
760
1100
W
2
SP601
Electrical Specifications
(V
BIAS
= 15V, Pulsed <300ms), Unless Otherwise Noted, All Parameters Referenced to V
SS
Except TRIP
U
,
CL2, G1U, D1U, and V
BS
Referenced to PHASE. D
F
: V
DF
to V
BS
, C
F
: V
BS
to PHASE
(Continued)
PARAMETER
SYMBOL
TEMP
MIN
TYP
MAX
UNITS
Upper/Lower Source Impedances (I
SOURCE
= 10mA)
R
SO L/U
+25
o
C
12
17
23
W
-40
o
C to +85
o
C
7
17
29
W
Upper/Lower Sink Impedances (I
SINK
= 10mA)
R
SI L/U
+25
o
C
8
12
16
W
-40
o
C to +85
o
C
5
12
20
W
Bootstrap Supply Current Limiting Impedance
R
BS
+25
o
C
2
3.5
5
W
-40
o
C to +85
o
C
1.4
3.5
5.6
W
Noise Dropping Resistor Impedance
R
ND
+25
o
C
6
10
14
W
-40
o
C to +85
o
C
5.4
10
14.6
W
High Voltage Leakage (500V V
BS
, V
OUT
, PHASE,
TRIP
U
, CL2, G1U, G2U, and D1U to V
SS
.
All other Pins at V
SS
)
I
LK
+25
o
C
-
1
3
m
A
Miller Clamp Diodes; D1U and D1L (I
D
= 10mA)
V
D1U/L
+25
o
C
0.4
0.9
1.4
V
Noise Clamping Zeners; CL2 and CL1 (I
Z
= 10mA)
V
CL2/1-LOW
+25
o
C
6.35
6.61
6.85
V
-40
o
C to +85
o
C
6.15
6.61
7.15
V
Noise Clamping Zeners; CL2 and CL1 (I
Z
= 50mA)
V
CL2/1-
HIGH
+25
o
C
7.0
8.5
8.0
V
V
OUT
Limiting Resistance
R
O
+25
o
C
2
3.5
5
W
-40
o
C to +85
o
C
1.4
3.5
5.6
W
NOTE: Maximum Steady State
¸
15V
DC
Supply Current = I
BIAS
L
¸
I
BS
Switching Specifications
(All Referenced to V
SS
, Except: TRIP
U
, Cl2, G1U, G2U, and D1U Referenced to PHASE.
D
F
: V
DF
to V
BS
, C
F
: V
BS
to PHASE)
PARAMETER
SYMBOL
TEMP
MIN
TYP
MAX
UNITS
Refresh One Shot Timer
t
REF
+25
o
C
200
350
500
m
s
-40
o
C to +85
o
C
180
350
540
m
s
Delay Time of Trip I/U Voltage (I
TRIPSEL
low) to
G2U/G2L Low (50% Overdrive
t
OFF
TN
+25
o
C
2
3
4
m
s
-40
o
C to +85
o
C
1.85
3
4.35
m
s
Delay Time of Trip I Voltage (I
TRIPSEL
low) to
Faultbar Low
t
FN
+25
o
C
2
3
4
m
s
-40
o
C to +85
o
C
1.85
3
4.35
m
s
Delay Time of Phase Out of Status to Faultbar
Low (TOP High)
t
OSVF
+25
o
C
500
700
900
ns
-40
o
C to +85
o
C
400
700
1050
ns
Minimum Logic Input Pulse Width: TOP and
BOTTOM
t
MINIW
+25
o
C
300
430
600
ns
-40
o
C to +85
o
C
275
430
660
ns
Minimum G1U/G1L On Time
t
ON
+25
o
C
1.6
2.3
3.1
m
s
-40
o
C to +85
o
C
1.5
2.4
3.4
m
s
Minimum Pulsed Off Time, G2U/G2L
t
OFF
+25
o
C
1.3
2.0
3.4
m
s
-40
o
C to +85
o
C
1.05
2.1
3.9
m
s
Turn On Delay Time of G1U (BISTATE MODE)
t
ON
D
+25
o
C
2.5
3.2
4.5
m
s
-40
o
C to +85
o
C
2.1
3.3
5.2
m
s
Turn On Delay Time of G1L (BISTATE MODE)
t
ON
D
+25
o
C
2.5
3.2
4.5
m
s
-40
o
C to +85
o
C
2.1
3.3
5.2
m
s
Turn On Delay Time of G1U
(THREE-STATE MODE)
t
ON
D
+25
o
C
0.75
1.0
1.5
m
s
-40
o
C to +85
o
C
0.60
1.1
1.75
m
s
3
SP601
Switching Specifications
(All Referenced to V
SS
, Except: TRIP
U
, Cl2, G1U, G2U, and D1U Referenced to PHASE.
D
F
: V
DF
to V
BS
, C
F
: V
BS
to PHASE)
(Continued)
PARAMETER
SYMBOL
TEMP
MIN
TYP
MAX
UNITS
Turn On Delay Time of G1L
(THREE-STATE MODE)
t
ON
D
+25
o
C
0.75
1.0
1.5
m
s
-40
o
C to +85
o
C
0.60
1.1
1.75
m
s
Turn Off Delay Time of G2U and G2L
t
OFF
D
+25
o
C
0.75
1.0
1.45
m
s
-40
o
C to +85
o
C
0.60
1.1
1.75
m
s
Minimum Dead Time: G1U OFF to G1L ON, or
G1L off to G1U on (BISTATE MODE)
t
D.T.
+25
o
C
1.5
2.5
3.5
m
s
-40
o
C to +85
o
C
1.2
2.6
4
m
s
Fault Reset Delay to Clear Faultbar
t
R.T.
+25
o
C
3.4
4.5
6.6
m
s
-40
o
C to +85
o
C
3.15
4.8
7.4
m
s
Rise Time of Upper and Lower Driver
(Load = 2000pF)
t
R U/L
+25
o
C
25
50
100
ns
-40
o
C to +85
o
C
15
50
115
ns
Fall Time of Upper and Lower Driver
(Load = 2000pF)
t
F U/L
+25
o
C
25
50
100
ns
-40
o
C to +85
o
C
15
50
115
ns
Recommended Operating Conditions and Functional Pin Description
(All Voltages Referenced to V
SS
, Unless
Otherwise Noted. See Figure 1)
PARAMETER
CONDITION
FAULTBAR
Open Drain Fault Indicator Output
I
TRIPSELECT
Digital Input Command to Increase TRIP
L
and TRIP
U
Threshold by 30%
V
BIAS
14.5V to 16.5V with 15V nominal,
@
1.5mA DC BIAS Current
V
DD
C
DD
to V
SS
V
SS
COMMON
TRIP I
100mV Signal to Shut Off LOWER Drive and Trigger a Fault Output
CL1
Lower Noise Clamp Zener
G2L and G1L
Low Impedance Driver Designed to Drive Power MOS Transistors (LOWER)
V
DF
Current Limiting Charging Resistor for Bootstrap Capacitor Power Supply
V
BS
Bootstrap Supply, Normally a Diode Drop Below V
DD
Voltage with Respect to the Floating PHASE Reference
V
OUT
Load Connection Node
PHASE
Floating Reference Point for High Side Control Circuitry: V
BS
, TRIP
U
, CL2, G1U, G2U and D1U
TRIP
U
100mV Signal, Referenced to PHASE, to Shut Off UPPER Drive
CL2
Upper Noise Clamp Zener
G2U and G1U
Low Impedance Driver Designed to Drive Power MOS Transistors (UPPER)
ENABLE
Digital Input to ENABLE the UP/DN Command to Turn on Top/Bottom Devices
UP/DN
Digital Input to Top/Bottom Device (If ENABLE is High)
D1U
Miller Clamp UPPER to V
BS
D1L
Miller Clamp LOWER to V
DD
4
SP601
Timing Diagram
ENABLE
1
0
1
0
1
0
1
ENABLE
1
UP/DOWN
UP/DOWN
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
V
DC
COM
REFRESH
ONE SHOT
REFRESH
ONE SHOT
I
ON
B
0
1
0
1
0
1
0
1
0
1
0
1
0
V
DC
COM
I
ON
B
VALID BOT
ON
VALID BOT
ON
I
OFF
T
I
OFF
T
I
ON
T
I
ON
T
I
OFF
B
I
OFF
B
UPPER
UPPER
LOWER
LOWER
V
OUT
V
OUT
THREE-STATE MODE SLOWER THAN REFRESH ONE SHOT TIMER
BISTATE MODE SLOWER THAN REFRESH ONE SHOT TIMER
NOTE: BOT switching not relevant.
Typical Circuit Configuration
TRUTH TABLE
Applicable to Typical Circuit Configuration (Figure 1)
INPUTS
OUTPUTS
UP/DN
ENABLE
TRIP
L
TRIP
U
PHASE
V
BIAS
UPPER
LOWER
FAULT BAR
0
0
0
X
X
1
0
0
1
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
0
0
1
1
0
X
0
1
0
0
0
X
X
1
X
X
1
0
0
0
0
1
0
X
X
1
0
1
1
1
0
0
X
X
1
0
0
1
X
X
X
X
X
0
0
0
0
NOTE: 0 = False, 1 = True, X = Don’t Care
5
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