ltc1155.pdf

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LTC1155
Dual High Side
Micropower MOSFET Driver
FEATURE
S
ESCRIPTIO
The LTC ® 1155 dual high side gate driver allows using low
cost N-channel FETs for high side switching applications.
An internal charge pump boosts the gate above the posi-
tive rail, fully enhancing an N-channel MOSFET with no
external components. Micropower operation, with 8
n
Fully Enhances N-Channel Power MOSFETs
n
8
m
A Standby Current
n
85
m
A ON Current
n
Short-Circuit Protection
n
Wide Power Supply Range: 4.5V to 18V
m
n
Controlled Switching ON and OFF Times
A operating current, allows use in
virtually all systems with maximum efficiency.
m
n
No External Charge Pump Components
n
Replaces P-Channel High Side MOSFETs
Included on-chip is overcurrent sensing to provide auto-
matic shutdown in case of short circuits. A time delay can
be added in series with the current sense to prevent false
triggering on high in-rush loads such as capacitors and
incandescent lamps.
n
Compatible with Standard Logic Families
n
Available in 8-Pin SO Package
A
PPLICATI
S
n
Laptop Power Bus Switching
The LTC1155 operates off of a 4.5V to 18V supply input
and safely drives the gates of virtually all FETs. The
LTC1155 is well suited for low voltage (battery-powered)
applications, particularly where micropower “sleep” op-
eration is required.
SCSI Termination Power Switching
n
Cellular Phone Power Management
n
n
P-Channel Switch Replacement
Relay and Solenoid Drivers
n
Low Frequency Half H-Bridge
n
The LTC1155 is available in both 8-pin PDIP and 8-pin SO
packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
n
Motor Speed and Torque Control
TYPICAL
A
PPLICATI
Laptop Computer Power Bus Switch with Short Circuit Protection
V S = 4.5V TO 5.5V
R SEN
0.02
C DLY
0.1
+
C DLY
0.1
R SEN
0.02
Switch Voltage Drop
10
µ
W
µ
µ
F
W
0.25
R DLY
100k
R DLY
100k
DS1
V S
DS2
0.20
*IRLR034
*IRLR034
G1
LTC1155
G2
5A
MAX
5A
MAX
0.15
TTL, CMOS INPUT
IN1
GND
IN2
TTL, CMOS INPUT
0.10
POWER BUS
0.05
P
SYSTEM
m
DISK
DRIVE
PRINTER,
ETC.
0.00
DISPLAY
0
1
2
3
OUTPUT CURRENT (A)
GND
1155 TA02
*SURFACE MOUNT
1155 TA01
1
D
A
standby current and 85
F
F
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LTC1155
A
BS O LUTEI
A
U
R
I S
G
(Note 1)
Supply Voltage ........................................................ 22V
Input Voltage ...................... (V S + 0.3V) to (GND – 0.3V)
Gate Voltage ......................... (V S +24V) to (GND – 0.3V)
Current (Any Pin) .................................................. 50mA
Storage Temperature Range ................. – 65
Operating Temperature Range
LTC1155C................................................ 0
°
C to 70
°
C
LTC1155I ........................................... – 40
°
C to 85
°
C
LTC1155M ........................................ – 55
°
C to 125
°
C
°
C to 150
C
Lead Temperature Range (Soldering, 10 sec.) ...... 300
°
C
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
TOP VIEW
ORDER PART
NUMBER
DS1
G1
GND
IN1
1
2
3
4
8
7
6
5
DS2
G2
V S
IN2
DS1
G1
GND
IN1
1
2
3
4
8
7
6
5
DS2
G2
V S
IN2
LTC1155CN8
LTC1155CJ8
LTC1155IN8
LTC1155MJ8
LTC1155CS8
LTC1155IS8
S8 PART MARKING
J8 PACKAGE
8-LEAD CERDIP
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
1155
1155I
T JMAX = 150 ° C, q JA = 100 ° C/W (J8)
T JMAX = 100 ° C, q JA = 130 ° C/W (N8)
T JMAX = 100 ° C, q JA = 150 ° C/W
E LECTR IC AL C
HARA TERIST ICS
C
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25
°
C.
V S = 4.5V to 18V, unless otherwise noted.
LTC1155M
LTC1155C/LTC1155I
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
V S
Supply Voltage
l
4.5
18
4.5
18
V
I Q
Quiescent Current OFF
V IN = 0V, V S = 5V (Note 2)
8
20
8
20
m
A
Quiescent Current ON
V S = 5V, V IN = 5V (Note 3)
85
120
85
120
m A
Quiescent Current ON
V S = 12V, V IN = 5V (Note 3)
180
400
180
400
m
A
V INH
Input High Voltage
l
2.0
2.0
V
V INL
Input Low Voltage
l
0.8
0.8
V
I IN
Input Current
0V < V IN < V S
l
1.0
±
1.0
m
A
C IN
Input Capacitance
5
5
pF
V SEN
Drain Sense Threshold Voltage
80
100
120
80
100
120
mV
l
75
100
125
75
100
125
mV
I SEN
Drain Sense Input Current
0V < V SEN < V S
± 0.1
± 0.1
m A
V GATE -V S
Gate Voltage Above Supply
V S = 5V
l
6.0
6.8
9.0
6.0
6.8
9.0
V
V S = 6V
l
7.5
8.5
15
7.5
8.5
15
V
V S = 12V
l
15
18
25
15
18
25
V
t ON
Turn ON Time
V S = 5V, C GATE = 1000pF
Time for V GATE > V S + 2V
50
250
750
50
250
750
m s
Time for V GATE > V S + 5V
200
1100 2000
200
1100 2000
m s
V S = 12V, C GATE = 1000pF
Time for V GATE > V S + 5V
50
180
500
50
180
500
m s
Time for V GATE > V S + 10V
120
450
1200
120
450
1200
m s
2
°
±
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LTC1155
ELECTRICAL C
HARA TERISTICS
C
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25
°
C.
V S = 4.5V to 18V, unless otherwise noted.
LTC1155M
LTC1155C/LTC1155I
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
t OFF
Turn OFF Time
V S = 5V, C GATE = 1000pF
Time for V GATE < 1V
10
36
60
10
36
60
m
s
V S = 12V, C GATE = 1000pF
Time for V GATE < 1V
10
26
60
10
26
60
m s
t SC
Short-Circuit Turn OFF Time
V S = 5V, C GATE = 1000pF
Time for V GATE < 1V
5
16
30
5
16
30
m s
V S = 12V, C GATE = 1000pF
Time for V GATE < 1V
5
16
30
5
16
30
m
s
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Quiescent current OFF is for both channels in OFF condition.
Note 3: Quiescent current ON is per driver and is measured independently.
TYPCALPERFOR
A
CE
C
HARA TERISTICS
C
Standby Supply Current
Supply Current/Side (ON)
High Side Gate Voltage
50
1000
24
V IN1 = V IN2 = 0V
T J = 25
V IN1 OR V IN2 = 2V
T J = 25 ° C
45
°
900
22
40
800
20
35
700
18
30
600
16
25
500
14
20
400
12
15
300
10
10
200
8
5
100
6
0
0
5
10
15
20
0
0
5
10
15
20
4
0
5
10
15
20
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
1155 G01
1155 G02
1155 TPC03
Input Threshold Voltage
Drain Sense Threshold Voltage
Low Side Gate Voltage
2.4
150
30
2.2
140
27
2.0
130
24
1.8
V ON
120
21
1.6
110
18
1.4
V OFF
100
15
1.2
90
12
1.0
80
9
0.8
70
6
0.6
60
3
0.4
50
0
0
5
10
15
20
0
5
10
15
20
0
2
4
6
8
10
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
1155 G04
1155 G05
1155 G06
3
C
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LTC1155
TYPCALPERFOR CE
A
C
HARA TERISTICS
C
Turn ON Time
Turn OFF Time
Short-Circuit Turn OFF Delay Time
1000
50
50
C GATE = 1000pF
C GATE = 100pF
TIME FOR V GATE < 1V
C GATE = 1000pF
TIME FOR V GATE < 1V
900
45
45
800
40
40
700
35
35
600
30
30
500
25
25
V SEN = V S –1V
NO EXTERNAL DELAY
400
20
20
V GS = 5V
300
15
15
200
10
10
V GS = 2V
100
5
5
0
0
0
0
5
10
15
20
0
5
10
15
20
0
5
10
15
20
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
1155 G07
1155 G08
1155 G09
Standby Supply Current
Supply Current Per Side (ON)
Input ON Threshold
50
1000
2.4
45
900
2.2
40
800
2.0
35
700
1.8
30
600
1.6
25
500
1.4
V S = 5V
20
400
1.2
V S = 18V
V S = 18V
15
300
1.0
V S = 12V
10
200
V S = 5V
0.8
5
V S = 5V
100
0.6
0
0
0.4
–50
– 25
0
25
50
75 100 125
–50
–25
0
25
50
75 100 125
–50
– 25
0
25
50
75 100 125
TEMPERATURE (
°
C)
TEMPERATURE ( ° C)
TEMPERATURE ( ° C)
1155 G10
1155 G11
1155 G12
PI N FU N CTIO N S
Input Pin
The LTC1155 logic input is a high impedance CMOS gate
and should be grounded when not in use. These input pins
have ESD protection diodes to ground and supply and,
therefore, should not be forced beyond the power supply
rails.
). Care should be taken to minimize any
loading of this pin by parasitic resistance to ground or
supply.
W
Supply Pin
The supply pin of the LTC1155 serves two vital purposes.
The first is obvious: it powers the input, gate drive,
regulation and protection circuitry. The second purpose is
less obvious: it provides a Kelvin connection to the top of
the two drain sense resistors for the internal 100mV
reference. The supply pin should be connected directly to
the power supply source as close as possible to the top of
the two sense resistors.
Gate Drive Pin
The gate drive pin is either driven to ground when the
switch is turned OFF or driven above the supply rail when
the switch is turned ON. This pin is a relatively high
impedance when driven above the rail (the equivalent of a
4
few hundred k
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LTC1155
PI N FU N CTIO N S
The supply pin of the LTC1155 should not be forced below
ground as this may result in permanent damage to the
device. A 300
W
This pin is also a high impedance CMOS gate with ESD
protection and, therefore, should not be forced beyond the
power supply rails. To defeat the over current protection,
short the drain sense to supply.
Drain Sense Pin
As noted previously, the drain sense pin is compared
against the supply pin voltage. If the voltage at this pin is
more than 100mV below the supply pin, the input latch will
be reset and the MOSFET gate will be quickly discharged.
Cycle the input to reset the short-circuit latch and turn the
MOSFET back on.
Some loads, such as large supply capacitors, lamps or
motors require high inrush currents. An RC time delay
must be added between the sense resistor and the drain
sense pin to ensure that the drain sense circuitry does not
false trigger during start-up. This time constant can be set
from a few microseconds to many seconds. However, very
long delays may put the MOSFET in risk of being destroyed
by a short-circuit condition (see Applications Information
section).
BLOCK
DAGRA
V S
ANALOG SECTION
DRAIN
SENSE
LOW STANDBY
CURRENT
REGULATOR
100mV
REFERENCE
COMP
s
DELAY
m
ANALOG
DIGITAL
GATE CHARGE
AND DISCHARGE
CONTROL LOGIC
GATE
TTL-TO-CMOS
CONVERTER
VOLTAGE
REGULATORS
R
INPUT
LATCH
IN
ONE
SHOT
S
OSCILLATOR
AND CHARGE
PUMP
FAST/SLOW
GATE CHARGE
LOGIC
GND
1155 BD
OPERATIO U
The LTC1155 contains two independent power MOSFET
gate drivers and protection circuits (refer to the Block
Diagram for details). Each half of the LTC1155 consists of
the following functional blocks:
to CMOS converter output enables the rest of the circuitry.
In this way the power consumption is kept to a minimum
in the standby mode.
Internal Voltage Regulation
The output of the TTL to CMOS converter drives two
regulated supplies which power the low voltage CMOS
logic and analog blocks. The regulator outputs are isolated
from each other so that the noise generated by the charge
pump logic is not coupled into the 100mV reference or the
analog comparator.
TTL and CMOS Compatible Inputs
Each driver input has been designed to accommodate a
wide range of logic families. The input threshold is set at
1.3V with approximately 100mV of hysteresis.
A voltage regulator with low standby current provides
continuous bias for the TTL to CMOS converters. The TTL
5
resistor should be inserted in series with
the ground pin if negative supply voltages are anticipated.
10
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