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Features
•
High-performance, Low-power Atmel
®
AVR
®
8-bit Microcontroller
Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20MIPS Throughput at 20MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
– 16/32/64/128KBytes of In-System Self-programmable Flash program memory
– 512/1K/2K/4KBytes EEPROM
– 1/2/4/16KBytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
– Data retention: 20 years at 85
°
C/ 100 years at 25
°
C
(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
QTouch
®
library support
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix acquisition
– Up to 64 sense channels
JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One/two 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel, 10-bit ADC
Differential mode with selectable gain at 1x, 10x or 200x
– Byte-oriented Two-wire Serial Interface
– Two Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and
Extended Standby
I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF
– 44-pad DRQFN
– 49-ball VFBGA
Operating Voltages
– 1.8 - 5.5V
Speed Grades
– 0 - 4MHz @ 1.8 - 5.5V
– 0 - 10MHz @ 2.7 - 5.5V
– 0 - 20MHz @ 4.5 - 5.5V
Power Consumption at 1MHz, 1.8V, 25
°
C
– Active: 0.4mA
– Power-down Mode: 0.1µA
– Power-save Mode: 0.6µA (Including 32kHz RTC)
8-bit Atmel
Microcontroller
with
16/32/64/128K
Bytes In-System
Programmable
Flash
ATmega164A
ATmega164PA
ATmega324A
ATmega324PA
ATmega644A
ATmega644PA
ATmega1284
ATmega1284P
8272C–AVR–06/11
Note:
1.
See
”Data Retention” on page 9
for details.
ATmega164A/PA/324A/PA/644A/PA/1284/P
1.
Pin Configurations
1.1
Pinout - PDIP/TQFP/VQFN/QFN/MLF for
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P
Figure 1-1.
Pinout
(PCINT8/XCK0/T0) PB0
(PCINT9/CLKO/T1) PB1
(PCINT10/INT2/AIN0) PB2
(PCINT11/OC0A/AIN1) PB3
(PCINT12/OC0B/SS) PB4
(PCINT13/ICP3/MOSI) PB5
(PCINT14/OC3A/MISO) PB6
(PCINT15/OC3B/SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(PCINT24/RXD0/T3) PD0
(PCINT25/TXD0) PD1
(PCINT26/RXD1/INT0) PD2
(PCINT27/TXD1/INT1) PD3
(PCINT28/XCK1/OC1B) PD4
(PCINT29/OC1A) PD5
(PCINT30/OC2B/ICP) PD6
PA0 (ADC0/PCINT0)
PA1 (ADC1/PCINT1)
PA2 (ADC2/PCINT2)
PA3 (ADC3/PCINT3)
PA4 (ADC4/PCINT4)
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6)
PA7 (ADC7/PCINT7)
AREF
GND
AVCC
PC7 (TOSC2/PCINT23)
PC6 (TOSC1/PCINT22)
PC5 (TDI/PCINT21)
PC4 (TDO/PCINT20)
PC3 (TMS/PCINT19)
PC2 (TCK/PCINT18)
PC1 (SDA/PCINT17)
PC0 (SCL/PCINT16)
PD7 (OC2A/PCINT31)
TQFP/QFN/MLF
(PCINT13/ICP3/MOSI) PB5
(PCINT14/OC3A/MISO) PB6
(PCINT15/OC3B/SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(PCINT24/RXD0/T3) PD0
(PCINT25/TXD0) PD1
(PCINT26/RXD1/INT0) PD2
PA4 (ADC4/PCINT4)
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6)
PA7 (ADC7/PCINT7)
AREF
GND
AVCC
PC7 (TOSC2/PCINT23)
PC6 (TOSC1/PCINT22)
PC5 (TDI/PCINT21)
PC4 (TDO/PCINT20)
Note:
The large center pad underneath the VQFN/QFN/MLF package should be soldered to ground on
the board to ensure good mechanical stability.
2
8272C–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
1.2
Pinout - DRQFN for ATmega164A/164PA/324A/324PA
Figure 1-2.
DRQFN - Pinout
Top view
Bottom view
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
A18
B15
A17
B14
A16
B13
A15
B12
A14
B11
A13
A18
B15
A17
B14
A16
B13
A15
B12
A14
B11
A13
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
Table 1-1.
DRQFN - Pinout
A1
PB5
A7
PD3
A13
PC4
A19
PA 3
B1
PB6
B6
PD4
B11
PC5
B16
PA 2
A2
PB7
A8
PD5
A14
PC6
A20
PA 1
B2
RESET
B7
PD6
B12
PC7
B17
PA 0
A3
VCC
A9
PD7
A15
AVCC
A21
VCC
B3
GND
B8
VCC
B13
GND
B18
GND
A4
XTAL2
A10
GND
A16
AREF
A22
PB0
B4
XTAL1
B9
PC0
B14
PA 7
B19
PB1
A5
PD0
A11
PC1
A17
PA 6
A23
PB2
B5
PD1
B10
PC2
B15
PA 5
B20
PB3
A6
PD2
A12
PC3
A18
PA 4
A24
PB4
3
8272C–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
1.3
Pinout - VFBGA for ATmega164A/164PA/324A/324PA
Figure 1-3.
VFBGA - Pinout
Top view
Bottom view
1
234567
765432
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
Table 1-2.
BGA - Pinout
1
2
3
4
5
6
7
A
GND
PB4
PB2
GND
VCC
PA2
GND
B
PB6
PB5
PB3
PB0
PA0
PA3
PA5
C
VCC
RESET
PB7
PB1
PA1
PA6
AREF
D
GND
XTAL2
PD0
GND
PA4
PA7
GND
E
XTAL1
PD1
PD5
PD7
PC5
PC7
AVCC
F
PD2
PD3
PD6
PC0
PC2
PC4
PC6
G
GND
PD4
VCC
GND
PC1
PC3
GND
4
8272C–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
2.
Overview
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a low-power CMOS 8-bit
microcontroller based on the AVR enhanced RISC architecture. By executing powerful instruc-
tions in a single clock cycle, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1.
Block Diagram
PA7..0
PB7..0
VCC
Power
Supervision
POR / BOD &
RESET
RESET
PORT A (8)
PORT B (8)
Watchdog
Timer
GND
A/D
Converter
Analog
Comparator
Watchdog
Oscillator
USART 0
XTAL1
Oscillator
Circuits /
Clock
Generation
Internal
Bandgap reference
EEPROM
SPI
XTAL2
8bit T/C 0
CPU
16bit T/C 1
16bit T/C 1
JTAG/OCD
8bit T/C 2
USART 1
TWI
FLASH
SRAM
16bit T/C 3
PORT C (8)
PORT D (8)
PD7..0
TOSC2/PC7
TOSC1/PC6
PC5..0
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than
conventional CISC microcontrollers.
5
8272C–AVR–06/11
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